I'm integrating this IP on a Cyclone V GX device (5CGXFC3B6F23I7) using Quartus Prime 23.1std.
My configuration is:
- Core Variation: "10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS"
- Uncheck "Use Internal FIFO"
- Transceiver Type: GXB
- Enable Timestamping
- Enable SGMII bridge
When generated, the IP presents specific signals for transceiver reconfiguration: reconfig_togxb and reconfig_fromgxb.
In the documentation of the IP, it says:
"For Arria V, Cyclone V, and Stratix V designs, Altera recommends that you instantiate the Transceiver Reconfiguration Controller megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation. The transceivers in the Arria V, Cyclone V, and Stratix V designs are configured with Altera Custom PHY IP. The Custom PHY IP requires two reconfiguration interfaces for external reconfiguration controller. For more information on the reconfiguration interfaces required, refer to the V-Series Transceiver PHY IP Core User Guide and the respective device user guides."
My questions are:
1. What happen if I don't instantiate this reconfiguration controller?
2. What do I do with these two signals reconfig_togxb and reconfig_fromgxb if I don't instantiate the reconfiguration controller?
3. If I instantiate this controller, what are the parameters in the IP configurator:
Number of reconfiguration interfaces: 2 (ok from documentation)
Enable duty configuration: Checked or not?
Enable Analog controls: Checked or not?
Enable channel/PLL reconfiguration: Checked or not?
Enable PLL reconfiguration support block: Checked or not?
Thanks for support
連結已複製
Hi Nicales,
The reconfig_togxb and reconfig_fromgxb are SERDES control signals and present in variations targeting devices with GX transceivers.
Its best to follow the recommendation to ensure the performance is maximized for the IP.
You may refer to below link to understand further more on XCVR reconfiguration
Regards,
Pavee
Hello,
My concern is not yet addressed.
My first message contained specific questions and I asked for answers because I couldn't find then in the Intel documents such as the one you give the link for.
Christophe
1. What happen if I don't instantiate this reconfiguration controller?
> The transceivers in the Cyclone V designs are configured with Altera Custom PHY IP. The Custom PHY IP requires two reconfiguration interfaces for external reconfiguration controller. That's the reason why this should instantiate.
2. What do I do with these two signals reconfig_togxb and reconfig_fromgxb if I don't instantiate the reconfiguration controller?
> Leave this bus disconnected if you are not using an external reconfiguration controller.
3. If I instantiate this controller, what are the parameters in the IP configurator:
Number of reconfiguration interfaces: 2 (ok from documentation)
Enable duty configuration: Checked or not?
> I'm not seeing this option in GUI, what Im seeing at my end is Enable duty cycle calibration.
Enable Analog controls: Checked or not?
> Turn on the Enable Analog controls option to enable VOD setting reconfiguration
Enable channel/PLL reconfiguration: Checked or not?
> Turn on the Enable channel/PLL reconfiguration option to allow the streamer-based reconfiguration process. This reconfiguration mode reconfigures the TX/RX data path, CDR settings, and TX PLL selection.
Enable PLL reconfiguration support block: Checked or not?
> Checked if only you enabled the Channel/PLL reconfiguration. When enabled, the Transceiver Reconfiguration Controller includes logic to perform PLL reconfiguration.
More information on this UG: https://www.intel.com/content/www/us/en/docs/programmable/683321/current/using-the-transceiver-reconfiguration.html
Hello,
We didn't hear from you since last update. If you have a new question, feel free to open a new thread to get the support from Altera experts.
Otherwise, the community users will continue to help you on this thread.
Thank you.
