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Triple Speed Ethernet with Cyclone III DSP Development Kit

Altera_Forum
Honored Contributor II
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Hi, 

 

I am trying to implement Triple Speed Ethernet module into my cyclone III but after several tries it does not work. This board includes Marvell 88E111 RGMII Interface PH-layer. I am not sure what it is my problem so I enumerate the steps I have followed: 

 

1. PLL with two clocks at 125 MHz with 180º of delay: one is connect to 'tx_clk' input of TSE block and the other to pin T8 (I have taken into account the indications of CIII Development Board Reference Manual). 

 

2. I have included the TSE block into my schematic with RGMII/MII and I have connected several ports to the indicated pinsfile:///C:/Users/Jajo/AppData/Local/Temp/moz-screenshot-2.jpg in the reference manual. 

  • tx_clk: 125MHz from PLL. 

  • tx_control: pin_aa7 (2.5v) 

  • rgmii_out
  • rgmii_in
  • rx_control: pin_ab4 (2.5v) 

  • rx_clk: pin_b14 (1.8v) 

  • set_10, m_rx_en, m_rx_err, m_rx_d
  • set_1000: vcc
is this enough? 

 

With signal tap I have tried to check different signal, such as ff_rx_a_empty but it is always 1 (I connected the ethernet port of the cyclone board to my computer and vlc is sending video stream to 255.255.255.255). 

 

Thanx
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Altera_Forum
Honored Contributor II
408 Views

You have to configure the registers in the TSE core to enable it.

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Altera_Forum
Honored Contributor II
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How do you initialize the TSE? Are you using a Nios CPU? 

180º phase shift for a DDR interface seems a lot. Are you sure it's the correct value? 

Did you add timing constraints to the design? 

Is the PHY chip properly initialized, and did the auto-negotiation work?
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Altera_Forum
Honored Contributor II
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#How do you initialize the TSE? Are you using a Nios CPU? 

180º phase shift for a DDR interface seems a lot. Are you sure it's the correct value? 

 

No, I do not use Nios CPU. 

 

Initialize ... well, that is my problem I do not know what steps I have to follow, except the physical connections. 

# Did you add timing constraints to the design? 

 

At this moment, no contraints. 

# Is the PHY chip properly initialized, and did the auto-negotiation work? 

 

... I am confused, I thought PHY chip is initalized by itself, could you be more specific?  

 

Thankx Daixiwen
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Altera_Forum
Honored Contributor II
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Have a look at the TSE datasheet, you have a list of registers. You should at least put it in gigabit mode, set up a mac address and a few other things. 

The timing constraints are mandatory at those speeds. You must constraint the GMII I/O or you'll have problems. 

The PHY is supposed to be properly initialized, but you can still read its MDIO registers through the TSE MAC to check that it detected the link and negotiated the correct speed.
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Altera_Forum
Honored Contributor II
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rx_clk: pin_b14 (1.8v) is wrong . In Cyclone 3 board schematic the rx_clk should have been connected to 2.5v bank. 

 

I Tried ,I not getting any clock on rx_clk pin.
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