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Honored Contributor I
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Triple Speed Ethernet with external fifo connection issues

I want to implement an 8 channel SGMII Triple Speed Ethernet design in SOPC, 

Stratix IV, uses SGMII out to GXB ports.  

 

I can implement a single channel design, no issues, connecting up to an sgdma core and then into the Nios system.  

 

In the Triple Speed Ethernet core settings I can set the number of channels to 8, but only if I deselect "Use internal FIFO".  

 

When I make that selection, it adds a number of new ports to the core: 

- receive fifo status (Avalon Streaming Sync) 

- receive_packet_type_nn (Avalon Streaming Source) 

 

Where do I connect these new ports? 

The User Guide says the "fill level of an external FIFO buffer is obtained via the Avalon-ST receive fifo status interface" 

 

If I instantiate any of the Avalon-ST fifos, they do not have an Avalon-ST interface output to provide the fill level. I can enable source and/or sink level fill level in the Avalon-ST Dual Clock FIFO, but that creates a non streaming Avalon memory mapped input which is expected to connect into the NIOS flat memory space.  

 

Is there a fifo or some adaptor I need to use to make this work? 

 

I suppose I could just implement 8 completely independent Triple Speed Ethernet cores with internal fifos, but that seems like a complete waste of resources, including flat memory space..
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Honored Contributor I
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Looks like I can not just create N number of independent SGMII channels in SOPC - unless each one is in it's own GX transceiver block: 

 

Here's why: 

 

- I created a single SGMII channel, wired it up in SOPC, generated the netlist, no problem.  

- at the netlist level it creates ports to connect up an altgx_reconfig block for the transceiver. It seems to generate the altgx_reconfig signals for up to four transceivers, even though I only set it to one SGMII port to avoid the external fifo problem I haven't worked out (see initial post).  

 

- if I wire it all up to an altgx_reconfig block, all is well.  

 

- I added three more independent SGMII ports in the same transceiver block in SOPC, EACH of them creates a new altgx_reconfig connection port, that is big enough for up to four GX channels.  

 

- I'm stuck with the wires for four full independent altgx_reconfig blocks at the top level, but all four GX ports are required to share one altgx_reconfig port. Trouble is, I can't wire all four into a single altgx_reconfig block, since the altgx_reconfig data port is only 16 bits wide (same width from 1 to 4 channels), and I have 4 each of 16 bits of reconfig data to connect to it. Fail! 

 

Looks like I'm stuck setting the individual SGMII block in SOPC back to 4 channels and trying to figure out how to wire the external fifo, with little or no documentation describing what fifo IP core to use.. 

 

Is there an SOPC reference design that uses more than a single SGMII channel in a GX block?
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Honored Contributor I
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I also can't seem to create an interface to the receive fifo status sink or the receive packet type source. Streaming adaptors do not work; I can not use them to interface between the 5 bits per symbol of the receive packet type and, for instance, the 8 bits per symbol o a scatter-gather DMA interface. Any help or insight will be much appreciated. My design of a 4-port triple speed interface is complete but for these two types of ports.

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