Triple speed MAC IP

[Altera_Forum]

Hi, 

 We are currently in a project where we are evaluating the possibility to use Altera's Triple speed MAC. We did a quick setup in SOPC Builder, generated the system, synthesized the design and analyzed it with TimeQuest.   TimeQuest reports a clock summary where several clock nets are found which we need to understand. The following nets are reported in the clock summary:   pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|CJQJ5354:AJQA6937|CLIA8751[18] pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_0 pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_1 pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_2 pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_3 pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_4 pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_5 pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_6 pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\cycloneiii_WCRO7487_gen_0:cycloneiii_WCRO7487_gen_1|EPEO2888_7   I suspect that these might originate from the host clock divisor for the MDIO module. But that's only a guess, it would be good to understand this fully so we can constrain the design properly.   Thanks!

[Altera_Forum]

Are you using the web edition? I saw this once before and nobody was ever able to explain it. Honestly I think it is a bug. When I moved the project to a subscription edition, these clocks went away. 

 Jake

[Altera_Forum]

Hi Jake, 

 Thanks for the reply. Yeah, we are using the web edition, 8.0SP1. I have put a service request on this, so I'll keep you updated as soon as I get the solution confirmed from Altera.

[Altera_Forum]

We have now tried using the subscription 8.1 of Quartus II. However, we still see the same result. There are 9 clock nets found in TimeQuest, according to above. 

 However, when using the triple speed MAC I think the altera_reserved JTAG pins are used, I found the below on the web:  "The altera_reserved_tck pin is automatically generated for a design that uses a JTAG accessible module such as the SignalTap® II logic analyzer, the In-System Memory Content Editor or the Nios® II debugger."  I suspect it has something to do with the JTAG accessible module above since the altera_reserved pins show up, but I cannot say for sure. I am in a discussion with Altera on this, so we have to wait and see what comes out from that discussion. I'll keep this updated as soon as I know more.   All advice are most welcome!

[Altera_Forum]

We have confirmed these unconstrained paths with Altera. They say this issue will be fixed in TSE 9.1.  

 I guess they will add constraints for these paths in this IP, or if they change the design to remove the paths completely. We have to wait for TSE 9.1 and see.   Anyway, we consider the issue to be solved. Good support from Altera (a guy named Jason) I must say!