Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,282 Views

Triple speed ethernet performance

Hello, 

is somewhere some application note like was AN440, where they were tested some types of ethernet applications and table with benchmark test results (in attachment AN440) ? 

 

I use DP83848 with IgorMac and uClinux driver, which is 10/100Mbps PHY and i would like to use new faster PHY. But I show to the table 4 (on 24 pages), where max. speed was 108Mbps for TX and 74Mbps for RX operation, it is not big motivation to choose another PHY.... 

 

Which PHY can you advise me ? How fast can you transmit and receive data on ethernet interface ?  

Before 3 years I tryed DK-DSP Stratix III board, but ethernet did not work with TSE and Marvell 88E1111 (it was connect for optical medium, i think and uclinux could not able to recognize it). 

 

Thank you for your answer. 

 

Jan Naceradsky
0 Kudos
11 Replies
Altera_Forum
Honored Contributor I
46 Views

The throughput restriction won't be caused by the MAC or PHY - that should be able to operate at line speed. 

The issue is running the IP network stack on a relatively slow cpu inside a large operating system. 

 

If you connect a Ge PHY then bursts of receive packets will probably overrun the receive fifo and cause lost packets. This could make it impossible to receive fragmented IP messages (eg long UDP datagrams). 

You may well find that even a cheap ethernet switch has more bufferring for converting Ge to 100M without packet loss.
Altera_Forum
Honored Contributor I
46 Views

I dont understand what you mean line speed. In 10Mbps is line speed 10Mbps in 100Mbps it is 100Mbps, in gigabit network thi is same, but it is only theoretical speed, which i am not able to succeed.  

But in real design - triple speed ethernet succeed some speed with fifo 4kB and another speed with fifo 16kB, with nios2/f on 60MHz and another speed with nios2/e on 20MHz. I understanded that it is not depend on PHY, but my question is, if somebody measured the speed of triple speed ethernet in some configuration (design) and which is max. speed ? 

In attached files was some measured values, but it seems me very low nad the document is old... 

 

Thank you.
Altera_Forum
Honored Contributor I
46 Views

How long is a piece of string? 

 

You can just about answer questions like: 

If I run linux kernel x.x.x compiled with options A, B and C, on a yyyMHz cpu with c kb of cache and m MB of SDRAM what throughput will will netperf version 2.6 give for a TCP transmit test when sending 8k blocks with Nagle disabled. 

 

Anything less specific can only be a guess.
Altera_Forum
Honored Contributor I
46 Views

I use NIOS2/f on 120MHz, it has 58BogoMIPS, 4kB data and instr.cache, 16MB SDRAM and when i used LAN91C111 i achieved for sending 64kB packet (sendto message) about 6MB/s (it is 48Mbps). Now when i use DP83848 which is 10/100Mbps PHY it will be same.  

But when i will use 88E1111 or someone else Micrel KSZ9021 10/100/1000Mbps, will i achieve speed about 60MB/s (480Mbps) ??? 

 

Netperf is command for testing performance in uclinux ?
Altera_Forum
Honored Contributor I
46 Views

It's not that simple. Systems using the TSE are very different than the ones using the LAN91C111 so it's not safe to assume that you will get the same performance with the DP83848. You need to try it. 

If you get a bandwidth that is sensibly lower than the PHY's theoretical limit (as in your example, 48Mbps on a 100Mbps phy), then you will probably get the exact same speed with a gigabit PHY. This kind of figure indicates that your speed is limited by the CPU side and not the PHY itself.
Altera_Forum
Honored Contributor I
46 Views

Yes, thank you very much. 

Now i understood this, i hope :). When i have the i/o operation of NIOS2/f on 120MHz, which take 68ns - 14,7MHz, so when i have 4-bits in RxD or TxD bus of PHy, it meens that max. teoretical speed is 14,7 x 4 = 58,8Mbps (7,3MB/s). 

Is it true ?
Altera_Forum
Honored Contributor I
46 Views

No it's not that simple. The CPU doesn't output the frames itself word by word. It uses a DMA. The packet emission part is actually quite fast (a DMA can usually read one word per cycle, so with the SGDMA clocked at 120MHz on a 32-bit bus, that would be a bit more than 3.8Gbits/s, if the memory can follow). What takes time is all the software processing by the IP stack, is much more difficult to estimate, and is very OS and (software) configuration dependant.

Altera_Forum
Honored Contributor I
46 Views

Okay. In this case it is suitable to use gigabit PHY. Marvell 88E1111 and 88E1145 are impossible to buy, so for TSE IP and driver for uClinux i need to use DP83865. For Micrel KSZ9021 i need to change uclinux driver... 

Do you know about some gigabit PHY for uClinux and its drivers ? 

Or is there some new ip core like was Igor Mac, but for gigabit ethernet ?
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

What takes time is all the software processing by the IP stack 

--- Quote End ---  

 

Yes, every data byte is touched multiple times during processing in the TCP/IP stack. As a result, NIOS based TCP speed hardly exceeds 100MBit/s. The better performance numbers in the application note aren't feasible without hardware acceleration, if I remember right. So besides specialized hardware TCP/IP stack solutions, a faster CPU like ARM SoC should be considered for true Gigabit speed.
Altera_Forum
Honored Contributor I
46 Views

Hi all,  

after 2 months i again returned to solving problem how to very quickly transfer data from fpga design to pc and again consider gigabit ethernet. I made some experiments and measurements of 10/100Mb ethernet chip, so i found that when i use LAN91C111 with NIOS2 i achieved about 60Mbps speed, but when i use MAC inside FPGA Igor Mac and have NIOS2 on 60MHz with PHY DP83848 and uClinux i achieved only 7Mbps. My collegue use NIOS2 on 100MHz and use only C "driver" without uClinux driver achived 14Mbps.  

But it is still slowly. 

Do you know if exist some design, which use NIOS2 only for configurating the external PHY and some fast hw., which can use the speed of PHY ... 100Mbps or 1000Mbps ? 

Or do you think that is better to use something like this kit 

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=167&no=816 

and use ARM processor inside FPGA ? 

 

Thank you very much for your answer.
Altera_Forum
Honored Contributor I
46 Views

You can check this example to see how to generate or receive UDP packets in hardware: http://www.alterawiki.com/wiki/nios_ii_udp_offload_example