UPSAMPLING BLOCK Problem

[Altera_Forum]

Hi guys, 

 has anyone experiences with the DSP Builder "UPSAMPLING BLOCK" ??? I want to use it but there is one big Problem: The Up Sampling block increases the output sample rate from the input sample rate. The output data is sampled every N cycles where N is equal to the up sampling rate. The output holds this value for 1 cycle, then for the next n-1 cycles the output is zero.  Compared to the DOWNSAMPLING BLOCK: The Down Sampling block decreases the output sample rate from the input sample rate. The output data is sampled at every N-th cycle where N is the down sampling rate. The output data is then held constant for the next n input cycles.  In my design I have to use this Up Sampling block but with the option to hold the output data constant.  Does anyone know how to solve this problem or how to built a selfmade Up Sampling block, please help.  T-4444 

[Altera_Forum]

This is just what "upsampling" does. It pads zeros to increase the sampling rate. If you want to reconstruct the samples, a lowpass filter or bandpass filter is needed.

[Altera_Forum]

No, for my design I need an Up Sampling block with the feature I wrote. I know other tools where you have the option to say "Copy Samples". If I use for example a 5x Up Sampling block, the first cycle is high and the following four are zero, but I need the follwowing cycles as high as the first. 

 Got anyone an idea how to get this work?

[Altera_Forum]

What you want then is not upsampling but "sample and hold". You don't need dsp builder to do that for you. All you need is an output sampling rate 5 times the input sampling rate. Then for every input sample produce 5 output samples that equal current input using basic logic. 

 True upsampling is to interpolate the input. One method is to insert zeros then low pass filter to remove freq copies introduced by zero insertion.

[Altera_Forum]

Yes you got it KAZ. but how to do this? I'm still beginner and need some extra help.

[Altera_Forum]

try this: 

The important thing is to keep data coming in at reduced rate   signal count :integer range 0 to 4:= 0;    in a clked process  if(count = 4) then count <= 0; enable <= '1'; else count <= count + 1; enable <= '0'; endif;    if(enable = '1') then data_out <= data_in; endif; 

[Altera_Forum]

Isn't there any way to do this in DSP Builder with some blocks? Because I got a big projekt completely done with DSP Builder and only this function is missing.

[Altera_Forum]

Just make it as a component and integrate your own component into DSP builder.

[Altera_Forum]

So please tell me how to do this exactly. As you read I'm brandnew to FPGA design.