Understanding the I/O setup for the Viterbi IP

[Altera_Forum]

I'm new to the forum and using the Viterbi IP. My application is using G1=171 and G2=133 with a constraint length L=7. I want to get to 3 soft bits but to get started we are using 1 soft bit or hard bit decision. I am feeding data from a convolutional encoder from a BERT 256 bit pattern so I know the input and output.  

 First, I am assuming an input to the convolutional encoder is 1 Mbps so the output of the convolutional encoder is 2 Mbps. I have set my bit sync to 2 Mbps that is feeding the Viterbi IP. My first question is do I feed the clock to the IP with 1 or 2 MHz. Second, for 1 soft bit decision, I am taking 2 bits from a delay line into the rr(2 downto 1) logic_vector. How do I know which is the first and second for the order?  I have been reading that I can turn on the BER feature and watch the numerrs to see if there are errors (I have no noise to start). I have tried to use the state_node_type to switch the barrel shifter and I see a difference but I don't get the correct data. Any suggestions?   I am then confused about the output rate for the data out of the IP. If I feed the clock in at 2 MHz from the above example, I see data changing at this rate which can not be true if the output is designed for the original 1 Mbps.   As any can see, I'm totally confused. I want to move to the 3 soft bits. My bit sync is digital so I am assuming that I move from the top bit to the top 3 bits and do the same as I am doing with 1 bit so if anyone can help me can moving, I would greatly appreciate the help.