Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
729 Views

Unexpected data write while connecting FPGA to PC via PCIe

Hello. 

 

I am tying to communicate between HostPC(Linux) and FPGA Board using PCI Express High Performance Reference Design (AN456). But I am observing unexpected data write to Endpoint memory on FPGA.  

I am using CentOS (kernel version 2.6.18-194.26.1.el5). 

 

I have successfully linked-up my FPGA Board to the HostPC. 

However , when I use SignalTap to observe waveform, I see unexpected data written to endpoint memory(EPMEM). 

Since EPMEM is located around endpoint of PCI bus, I decided to replace EPMEM with logic I designed. 

 

But before I install my own driver, I observed waveform again, now with reference driver uninstalled. 

Since no driver is installed I expected no data write, but unexpected data write was still observed. 

This unexpected data write may destroy the necessary data. 

 

This data write occurs very frequently. Unexpected 1DW is written every 4DW address. 

Whenever I operate a USB-connected mouse, "0x32" is written. 

Also, for unknown reason, "0x42" is written regularly, once around every 1 minute.  

 

I am not sure if these issues are caused by the Linux kernel or FPGA design itself... 

 

Thank you for your advice!
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
37 Views

Are they memory writes or IO writes? It might help if you post the bytes of the TLP from your signaltap trace.

Altera_Forum
Honored Contributor I
37 Views

I'm also using chaining dma which is generated by pcie megacore function. According Ip compiler for user guider,the data is stored in shared memory in the Root Complex.But there many problems to find how the data are transmitted.

Reply