I'm using the UniPHY for a DDR2 application in a Stratix IV. When I simulate the example project, I get a bunch of warnings along the lines of:
Warning-[PCWM-W] Port connection width mismatch
../rtl/uphy_altdqdqs.sv, 787
" stratixiv_delay_chain genblk6.genblk3.oct_delay_2( .datain (genblk6.genblk3.delayed_os_oct_1), .delayctrlin (octdelaysetting2[0]), .dataout (genblk6.delayed_os_oct));"
The following 3-bit expression is connected to 4-bit port "delayctrlin" of
module "stratixiv_delay_chain", instance "genblk6.genblk3.oct_delay_2".
Expression: octdelaysetting2[0]
In possibly related news, the simulation fails in calibration. Has anyone else seen these warnings?
