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Altera_Forum
Honored Contributor I
1,286 Views

Using VIP suite for Up-Scaling.

Hello, 

 

I am using VIP suite and SDI Ip core for converting DVI video input to 3G-SDI video output for sending video to long distance (150 mtrs). 

For the input DVI resolution 1600X1200 @60Hz, Pixel-clk:162MHz, i am successful in converting to SDI Video output. 

But for the DVI input resolution 1280X1024 @60Hz,Pixel-clk: 108MHz, some issues are coming in VIP suite Scaler MegaCore function. 

My design consist of Cyclone IV GX series FPGA and input-output flow as described below: 

 

dvi video input --> clocked video input --> scaler --> color space conversion --> chroma resampler --> clocked video output. 

(24bits-RGB, Hsync,Vsync, (1280X1024 to 

Active pixel, Pixel Clock ) 1920X1080p ) 

 

The Output of clocked video output Megacore function fed to SDI IP core. 

This same flow for 1600X1200 resolution is working but when i configure for 1280X1024 resolution, output is coming only first few lines. 

I believe this is due to overflow as it is setting to '1', but overflow for 1600x1200 is also there but it is working. 

Can anyone suggest, is their any limitation in Scaling by using VIP suite. 

 

Thank you 

 

Keshav
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4 Replies
Altera_Forum
Honored Contributor I
32 Views

This is a clocking problem -- what are you using for your clock to the image pipeline? If you're upscaling to 1600x1200, is the clock you're using to clock the scaler fast enough to generate pixels at the rate required for that resolution at 60hz? Even if it's running a different (faster) clock to the DVI clock, you may still be starving the scaler, as you're waiting for the next pixel. Normally you'd add a frame buffer somewhere.

Altera_Forum
Honored Contributor I
32 Views

See "Overflow" on page 11-7 of http://www.altera.com/literature/ug/ug_vip.pdf 

 

In your system, Scaler will assert backpressure as it outputs the pixels between 1280 and 1920 on each line. The first few lines work OK because the FIFO hasn't filled up yet. 

 

As fpgajeg mentioned, you can solve it with different clocks and/or frame buffer.
Altera_Forum
Honored Contributor I
32 Views

Thank you sir for replying. 

But sir in my design i have no external RAM, so i am restricted to use frame buffer MegaCore function. 

Can you please let me know, what could be the FIFO depth which can be used in CVI(Clocked video input) and CVO(Clocked video output). 

design flow as below: 

DVI -------> CVI --------> Scalar ---------> CSC ------------>CR----------->CVO 

(1280X1024@60Hz (1920X1080@60Hz 

Pclk-108MHz) Clk-148.5MHz) 

 

Here Sir, i used Bridge Clock @148.5MHz.  

So sir Is there any way without using frame buffer to solve this clock timing problem, by using only FPGA(cyclone iv gx) inbuilt memory? 

 

Thank you 

 

Keshav
Altera_Forum
Honored Contributor I
32 Views

Thank you sir for replying. 

But sir in my design i have no external RAM, so i am restricted to use frame buffer MegaCore function. 

Can you please let me know, what could be the FIFO depth which can be used in CVI(Clocked video input) and CVO(Clocked video output). 

design flow as below: 

DVI -------> CVI --------> Scalar ---------> CSC ------------>CR----------->CVO 

(1280X1024@60Hz (1920X1080@60Hz 

Pclk-108MHz) Clk-148.5MHz) 

 

Here Sir, i used Bridge Clock @148.5MHz. 

So sir Is there any way without using frame buffer to solve this clock timing problem, by using only FPGA(cyclone iv gx) inbuilt memory? 

 

Thank you 

 

Keshav
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