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Using multiple LPMs of same type but different characteristics

Altera_Forum
Honored Contributor I
737 Views

Hi all, 

 

I was trying to find a way to use the sam LPM Megafunction but with different settings. For example, the lpm_add_sub function, I would like to have both an adder and subtractor but can't figure it out. 

 

- Here's an example 

 

COMPONENT lpm_sub 

GENERIC ( lpm_direction : STRING := "ADD"; 

lpm_hint : STRING := "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"; 

lpm_representation : STRING := "SIGNED"; 

lpm_type : STRING := "LPM_ADD_SUB"; 

lpm_width : NATURAL := 32 

); 

PORT ( dataa : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 

datab : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 

result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 

); 

END COMPONENT; 

 

- and then instantiate it with: 

 

lpm_sub_component : lpm_sub 

PORT MAP ( a, c, result_sub ); 

 

- I get 

 

Error: Node instance "lpm_sub_component" instantiates undefined entity "lpm_sub" 

 

So it appears the component name has to be that of the lpm function. What is the use of the LPM_TYPE characteristic then? 

 

Thanks
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
55 Views

At some point the compiler will search for the entity "lpm_sub", which you probably haven't created as you want to invoke an existing LPM function. Hence the error. 

 

LPM_TYPE is to be seen as a constant rather than a parameter. LPM functions go back a long time, at some point it was an industry standard. 

 

You could do it like this 

library lpm ; use lpm.lpm_components.all ; - - - lpm_sub_component1 : lpm_add_sub generic map ( lpm_direction : STRING := "ADD"; . . . ) port map ( . . . ) ; lpm_sub_component2 : lpm_add_sub generic map ( lpm_direction : STRING := "SUB"; . . . ) port map ( . . . ) ;
Altera_Forum
Honored Contributor I
55 Views

That works, thanks!

Altera_Forum
Honored Contributor I
55 Views

even simpler, use behavioural VHDL: 

 

c <= a + b; 

f <= d - e; 

 

etc.
Altera_Forum
Honored Contributor I
55 Views

 

--- Quote Start ---  

even simpler, use behavioural VHDL: 

 

c <= a + b; 

f <= d - e; 

 

etc. 

--- Quote End ---  

 

 

 

yes it is a lot less typing and I do it that way almost always, but that wasn't the question ... necsup was contemplating LPM-functionality in general
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