I've been using this technique for several months, and I'm curious if anyone else does the same or if there is a better way.
When I want to track a signal in SignalTap, I do the following:
- Add a RegOut block to my model and give it a name like "DebugFIFODataOut".
- Generate DSP Builder, Qsys, and run Synthesis
- In SignalTap, search for *debugfifodataout* with filter set to Design Entry (all names).
- Drill down to the busSlaveFabric_*
- Insert the in_AMMregisterPortData* and in_AMMregisterPortWriteEn*
- Add meaningful Aliases to the signals
Note that you can use the write signal on the register as well as you are not actually concerned with register itself.
