FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5988 Discussions

Using signed binary fractional (SBF) in HIL

Altera_Forum
Honored Contributor II
1,220 Views

Hello! 

 

In my hardwar-in-loop (HIL) design, I am trying to give input in signed binary fractional (SBF) format, which is one of the options ( also provided for IOs), available at function level. After putting the HIL block in the design and replacing all other functions, it again requires to specify some rules on I/Os. Here it only provides option for signed or unsigned. 

I could not find any way to specify the bus type as SBF in the settings before configuring the device for my HIL. I think, as a result I can not get the proper result rather it turns to 0. 

 

Please help me out!!! 

Thanks very much!!! 

Regards-
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
130 Views

When you select each port in the HIL GUI, there should be < and > buttons to the right of the bit width which allow you to move the binary point.

Altera_Forum
Honored Contributor II
130 Views

Thank you sir... great!!! 

 

dunno why couldn't recognize before.... 

once again thank you!!!
Reply