Using the FFT Megfunction with the Nios II

[Altera_Forum]

Hello, 

 I already read all the related threads in this forum and the Nios forum etc. but these threads didn't helped me to solve my problem.   The goal is to connect an instance of the FFT IP-core created with the megawizard. Since the Cyclone III FPGA I'm using has limited resources, the module shall be as small as possible. For the first shot the performance is irrelevant.    I'm using Quartus II 8.1 and the Nios II IDE 8.1.   Thus I chose a 1024 point FFT mit 16bit data width and 16bit twiddle factor. I selected the burst architecture with a single output.   I simulated the generated core with the VHO file and the testbench created by the wizard. Up to here everythings fine.    Now I want to connect the IP-core to the Nios II. The streaming interface of the FFT IP-core has two 16bit inputs (imag and real) and three outputs (16bit real, 16bit imag, 6bit exponent). The default streaming interface only supports one data port. Therefore I wrote a wrapper that merges imag and real signals to a 32bit bus on the input and the output. The exponent output only need to be read once at the end of the FFT calculation. Thus I registered the ourput and added a seperate Avalon-MemoryMapped Slave interface to read the result.   Then I connected the avalon slave output to the Nios II data master port. The Streaming sink and Streaming source interfaces are connected to two SGDMA controller.    ext.SRAM --> SGDMA1 --> FFT Wrapper --> DGDMA2 --> ext.SRAM   SGDMA1 out port (source) --> FFT Wrapper(sink) / FFT Wrapper(source) --> SGDMA2 in port(sink)   All residual interfaces of the SGDMAs are conncted to a tristate bridge which in turn is connected to an external SRAM.    By the way I chose the SGDMA design example from Altera as reference.    There are several problems at this point. 1. I can't simulate my wrapper, because Modelsim can not bound the the FFTwrapper instance referring to the error message. 2. Transmitting data to the FFTwrapper seems to work in during the debug mode. An interrupt is released indicating the chain has been processed. The number of transfered bytes is correct (here 4096Bytes) if I check the status of the descriptor. BUT the receive decriptor, using the second SGDMA, stays busy. It seems to get no "end of packet" signal from the FFTwrapper.  3. The third problem is that Signaltap does not trigger any of the control signals, either of SGDMA1 or SGDMA2, also if the there is a succesful transmission indicated by an interrupt in the soft, running in debug mode.   Does anybody can help me. Maybe someone already used an Altera FFT IP-core with the Nios II or together with SGDMAs.    Example Designs would be very nice.