VIP Clocked Video Input Seperate Sync Timing Tolerance

[Altera_Forum]

Hello All, 

 - I'm running analog video to a TI TVP7002, which decodes it into 24 bit digital clocked video with seperate syncs. My output is a vanilla parallel TTL interface SVGA LCD. Plan is to use the FPGA SOPC for scaling and filtering. - All hooked up to the EP3C25 on the Cyclone III starter board, thorugh a Bitec breakout board, all connectivity verified - Video inputs are ADC'd then enter the FPGA, then into a Clocked Video Input block, generated through the SOPC builder. This is where my problems start; nothing seems to get through the clocked video input.  Observations: 1) If I connect the signals straight through the FPGA to my LCD target with no processing by the VIP or other logic: The system works, I see the video signal from the generator hardware 2) If in the SOPC I use: test pattern gen --> clocked video output , I see a perfect test pattern 3) If in the SOPC I use: test pattern gen --> frame buffer (DDR) --> clocked video output, I see a perfect test pattern 4) Any time I try to use the Clocked Video Input, nothing works.  Notes: 1) All sync signals are +ve polarity (HS, VS, DE) 2) The clock is clean 3) Input Signal Timings (After ADC by TVP7002): Pclk 50MHz HS 47KHz VS 75Hz HS width 32 pixels HBP 47 pixels HFP 2 pixels VS width 0 lines, 3 pixels VBP 0 LINES, 65 pixels VFP 0 Lines, 18 pixels 4) Analog side is a vanilla VESA 800x600 75Hz signal 5) Clocked Video Input is setup: Vid in and Vid out do NOT use same clock (50Mhz input pclk, VIP on 200Mhz) Seperate Sync Selected Control port is disabled  Questions: 1) Are there any restrictions on the video signal that the Clocked video INput will accept? What Porch settings, sync widths will it take? There's no mention of these in the literature.  2) What frequency does the Clocked Video INput need to be driven at to read the incoming video - 1x the PCLK? 2x the PCLK? 4x?? 3) There is mention of the Clocked Video Input block being turned 'off' by default in the literature. Is this only when the Control Port is enabled? Will it always work without the control port? 4) In general there is no mention of the clock ratios needed in the SOPC blocks, are they all single cycle blocks? Where can I find this literature?  Thanks in advance for all your help guys... Brent from Sydney, Australia.

[Altera_Forum]

Are you asserting the vid_locked signal of the clocked video input?

[Altera_Forum]

Good question, i forgot to mention: 

1) Locked is tied to VCC 2) vid_f is tied to GND

[Altera_Forum]

Are you sure your input video timings are correct? Normally, the vertical sync and porches would be measured in lines, not pixels. 

 Is the TVP7002 configured to output a data enable signal? A quick scan of the data sheet shows the FIDOUT pin can be configured to be data enable among other choices.  Are you sure the clocked video input is connected to the DATACLK output of the VXP7002 and not some other clock?

[Altera_Forum]

Hi Kevin, Thanks for your help so far. 

 The timings work when I connect the TVP7002 directly to the LCD. So this confirms that the clock is the correct clock too. Yes the short vertical porches are a concern; I'm going to see if I can enlarge them - but I don't think that's the issue as they are still plenty wide to trigger the timer that would be used in the clocked video input.  I have the FIDOUT configured for Data Enable, with about HFP = HBP = 20px or so.

[Altera_Forum]

--- Quote Start ---  I have the FIDOUT configured for Data Enable, with about HFP = HBP = 20px or so.  --- Quote End ---  The "or so" part doesn't sound very confident. You list different horizontal porch values in your original post. Unless you have a frame buffer, the input and output video timings must be perfectly synchronous with each other or else you will have problems.  What else is in your chain when testing the clocked video input? Have you tried using just clocked video in and clocked video out both using the same 50Mhz video clock?    --- Quote Start ---  4) In general there is no mention of the clock ratios needed in the SOPC blocks, are they all single cycle blocks? Where can I find this literature?  --- Quote End ---  Try looking in the section "Stall Behavior".

[Altera_Forum]

I have just looped back the LCD output from the SoPC to the input, and made an ad-hoc signal generator with a 24 bit binary counter. this is giving me a signal. this would indicate that I do indeed have a problem with my input signals not meeting the requirements of the vip.

[Altera_Forum]

The "or so" part doesn't sound very confident. You list different horizontal porch values in your original post. Unless you have a frame buffer, the input and output video timings must be perfectly synchronous with each other or else you will have problems. 

 The 'or so' is because i tried a stack of different values by programming them into the tvp7002; none changed the behaviour.  I've tried with a frame buffer to no avail.  What else is in your chain when testing the clocked video input? Have you tried using just clocked video in and clocked video out both using the same 50Mhz video clock?  Yeah, I just did a loop back with a counter to generate a signal and suprise! It works. I'll add the frame buffer back in and then try to get the signals from the TVP to work again. They must have a problem, some kind of incompatibility.  You've been a good help, thanks.

[Altera_Forum]

First thing I'd try is signaltap and look at the vsync,hsync, and data enable. If that data enable isn't working right, the clocked video input will choke. 

 You could try using embedded syncs instead. Also, I would connect up to the control port on the clocked video input and see what it's claiming.  Jake