VIP Scaler II run-time writeable coefficients

[RGH_Z]

We have been successfully using the VIP Scaler II with default compile-time coefficients for several years. Due to additional customer requirements we later (2019) tried to implement run-time coefficients, but were unsuccessful in the limited schedule available, and punted to compile-time alternatives as a necessary expedient. Now for new products/customers we are needing to try again, using a Verilog state machine in our code to write to the Avalon-MM control port at the start of each frame, e.g., as described in the Video and Image Processing User Guide, UG-VIPSUITE 2016.05.02, section 17.

We now appear to have everything ALMOST working properly, but are seeing distortions in resulting imagery which seem likely to be resulting from some possible scrambling of coefficient data, in/after the writing process (more details can be provided as needed).

As near as we can tell (e.g., using SignalTap, etc.), we appear to be properly formulating and writing the appropriate coefficients, but we aren't aware of a way for us to directly see how they are being received inside the IP. At the same time, there are concerns that the UG may not be very complete in further details of the writing process, and that it appears in some ways to be confusing and or self-contradictory.

We are wondering if there might be any additional documentation or other resources we might refer to or draw upon, if others might have been more successful in implementing a process of this sort, if there are any applicable errata for the UG (we have found no updates), and/or if there might be any applicable known bugs in the IP (and corresponding patches or workarounds).

We truly would greatly appreciate any help/verification/correction of our detailed implementation of that process which you might be able to provide.

(Note:  The required label ("Interface Protocol - Display Port|HDMI") doesn't seem quite appropriate, but was the closest in the limited list provided.)

[wchiah]

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate and get back to you soon. Thanks for your patience.

Best regards,

Wincent_Intel

[RGH_Z]

Thanks; just let me know what other info you might want, and what else I might be able to do.

[kieroonturk]

Hi,

In terms of additional resources to help check if your coefficient update method is correct, have you looked at the coefficient software drivers that are supplied in some of the design examples? This one for instance: https://www.intel.com/content/www/us/en/design-example/714758/intel-arria-10-fpga-intel-8k-displayport-video-format-conversion-design-example.html 

The software uses C++ drivers for each VIP core. The source code for each driver will be included in the Nios II BSP for the design (run the compile to generate it), and the scaler's source code includes functions to generate a load coefficients. You say that you are using  a verilog state machine to do this, so the software is not something you can just use directly, but it should be a good additional guide as to which registers need to be written and with what values to successfully load new coefficients.

If this is no help and you are still having problems then perhaps you could upload a screenshot of the scaler parameter set, and maybe some signaltap screengrabs that show the update in progress?

Thanks

[RGH_Z]

Thanks very much for the hints, and for jumping in, it is VERY much appreciated.

Based on continuing experimentation here (and on various hints, too), I think I have determined that we were writing coefficients properly/effectively, but the coefficients were in fact scrambled; in particular, it seems that we were writing the taps in inverse order from what the IP was expecting -- based on trying to follow the apparent ordering in the Megawizard-generated .mifs which resulted from using default coefficients at compile time.  I swapped that ordering, and am now getting desired/expected results.  I still plan to refer to the way they are being written in the design example you pointed me to (haven't taken the steps in that path yet, but want to cement my understanding better).

I had also started an IPS ticket (at the suggestion of our distributor rep), also being concerned about some of the apparent strangeness in the VIP User Guide; I still/now think that there may be issues there (which had also caused me to doubt if we were writing things correctly), but I will perhaps take those up further in that venue.

So I think I might be off and running now -- assuming I don't run into something else (in which case, I may have to return here, but after I bang my head again for a while)...

Many thanks again!

[RGH_Z]

Aha -- I see that you've also been in contact with the IPS side...

[wchiah]

Hi Rick,

Thank for reaching Altera Support, I believe the question you ask had been address by Kieron in here and Shawnna in IPS case #00886417.

A request to the documentation owner to also update the diagram or at least provide a note to reflect the Nv - 1 taps correction in Work In Progress. 

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Wincent_Intel

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