FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Video synchronism signals on DisplayPort

Honored Contributor II


I've already developed a few projects involving video standards but I am new to DisplayPort. I was looking at Altera IP documentation and I was wondering if it would be possible to use the IP to transfer images between two FPGAs in a situation where the frame rate is not regular. I mean that the image format is constant and that front/back porch are constant but the time from a frame to another may vary so it would be like to have a variable vertical blanking. 

I've read that newer versions of the standard contains an optional part for adaptive sync but I could not find any mention to this in the IP documentaion. Anyway being DisplayPort a packet oriented standard as far as I understood and being this implementation not directed to a monitor but between FPGAs, it may work. 

Does anyone has some piece of information or experience with Altera DisplayPort IP that hints it will not work? 

Thanks in advance. 


Best Regards, 

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