Warning: set_interface_assignment: Interface "hps_io" does not exist

[Joakim]

I'm trying to create an interface to my DDR3 memory connected to the HPS on a Cyclone V.

In platform designer I get the warning

"Warning: set_interface_assignment: Interface "hps_io" does not exist"

What does it mean?

Looking in the hierarchy view, I can see that it is related to the memory signals which makes me worried.

I have the HPS up and running, but it seems like the memory can't be accessed. I use a bidirectional avalon bus to the memory, where the signal sdram_waitrequest is constantly high.

From the SOC debugger I can't see the memory and the debugger just hangs if I try to access the area where I suspect that the memory should be.

Is this related to the warning?

[EBERLAZARE_I_Intel]

What are the specs for the DDR3 memory that you are using? And what particular FPGA board that you are working on?

[Joakim]

I'm using a Micron DDR3L SDRAM MT41K64M16 . Since this is not available in the HPS component, I have selected MT41J64M16 and modified the voltage to 1.35V.

I have updated the input clock to 50MHz, (Clock 2 is not used, but I found no way to disable it, so it is also set to 50 MHz).

Apart from this I believe that it is default settings.

The board is my own design using Cyclone V 5CSEMA5F31C6.

[Joakim]

I managed to get rid of the hps_io does not exist message, by adding the uart0 pins to HPS I/O Set 1. This also make the preloader continue executing, instead of hanging in the uart initialization.

Also noticed that I need to use the same name at the top level as the name used in the hps exported conduit, or there will be no pins assigned (without error).

But in the pin planner I can see a potential problem.

The differential pins are not assigned as a pair. e.g. mem_ck is paired with mem_ck(n) instead of mem_ck_n.

Is this something to worry about? At least they are assigned to the correct pins.

[EBERLAZARE_I_Intel]

Regarding the differential pins, can you take a look at this link? It might help you; https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd11032010_811.html