FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5744 Discussions

What does the arbitration look like for multiple masters to a single slave on an Avalon MM bus?

AThom47
Novice
228 Views

Hi,

 

I am trying to find out what the arbitration looks like when there are several masters accessing a single slave on an Avalon MM bus. I found some old information online (AN184) that describes this for SOPC builder and that there are arbitration assignments that can be set for each master slave pair. However I do not find any information about how this works or where I would set arbitration assignments in platform designer.

 

The only reference I found in the current Avalon Interface Specification is about a lock signal that is optional that will keep bus access to one master as long as it is not done with a burst access.

 

My specific platform designer example looks like this:

 

  1. emif interface to a DDR4 memory that has one Avalon MM slave interface
  2. 3 Avalon-MM Pipeline bridges that each have a master and a slave port
  3. all 3 pipeline master ports are connected to the one emif Avalon-MM slave port
  4. all 3 pipeline slave ports are exported so that they can be connected to custom Avalon-MM masters outside of the platform designer module

 

My specific questions are:

 

  1. If all 3 masters try to access the bus, who will be granted access first?
  2. If the master is starting a burst access indicated by the burstcount signal of more than 1, does the master keep access until the burst is done before the next master gets access? From the Avalon Interface Specification it sounds like this would require a lock signal but neither the emif avalon slave interface nor any of the pipeline bridges contain such a signal.
  3. Once one master is done with it's access who gets access to the bus next?
  4. Are there any settings that control the arbitration, and if yes, where are those located?

 

Any pointers to where this is documented or existing training or examples are greatly appreciated.

 

Thanks!

0 Kudos
1 Reply
KennyT_Intel
Moderator
97 Views

For question 1,3,4, you can refer to

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer... page 136 arbitration.

 

For question 2,

If the master is starting a burst access indicated by the burstcount signal of more than 1, does the master keep access until the burst is done before the next master gets access?

 

Yes, basically, they should be waitrequest/valid when u assert the burst. you can refer to the link above page 101.

Reply