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What should be the maximum port data width of DDR3 Uniphyfor DDR3 MT41J128M16 SDRAM?

Altera_Forum
Honored Contributor II
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1) I am using DDR3 SDRAM MT41J128M16HA of micron and to control this SDRAM I am using DDR3 SDRAM controller with Uniphy in Cyclone V (5CEFA7F31C7) FPGA (Hard External memory Interface, Full rate avalon interface, and total interface width = 16 or 32)  

To test this memory I used the example design give by altera which is generated along with the IP instantiation. While generating this example design I set the Port width in "controller setting" as 32, 64, 128. So the example design work correctly for the 32 and 64 bit port width. But for 128 bit width I get only "local_init_done" and "local_cal_success" signal asserted no read write is happening in the memory.  

I) So Please let me know what could be the problem? II) What should be the maximum port width I can use for given memory?  

 

2) For the 32 bit port width (avalon interface width) and with the burst_length = 1, the 32 bit data is written and read-back from the memory but to write next data I have to increment the address by 4, WHY?  

 

3) With the same 32 bit port width (avalon interface width) when I write the data only 2 half words are written but the DDR3 SDRAM MT41J128M16HA has fixed burst length of 8 so how this data get written into the memory ? what happen to the remaining burst of the DDR3? Is controller write some garbage value at the remaining burst ?
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