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Valued Contributor III
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Where is data stored in the PCI chaining dma reference design?

After adding a PCIe megafunction, a chaining dma reference design is generated by Quartus. I use it with the altpciechdma driver (I am on linux), and the DMA test seems to work fine. 

 

However, I cannot seem to figure out where the data is actually stored. 

 

In the driver code I read this: 

 

* The reference design does not have readable locations and thus a 

* dummy read, used to flush PCI posted writes, cannot be performed. 

 

However, the reference design says it uses the FPGA's internal memory. 

Is it just the FIFO that's implemented or is there a location where I can actually see the data that was transferred? 

 

Thank you!
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Valued Contributor III
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I have the same question.Looking for help!!

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Valued Contributor III
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* The reference design does not have readable locations and thus a 

* dummy read, used to flush PCI posted writes, cannot be performed. 

 

I am still confused about this part. I don't know what it means. 

But I figured out the data is stored in an altsyncram megafunction in the DMA arbiter module (look at the hierarchy).
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