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Where is the legacy interrupt enable/disable flag?

SimonRichter
New Contributor I
335 Views

I'm trying to trigger an interrupt from a CycloneIV GX, using either an MSI if available, or a legacy interrupt. I've found the "MSI master enable" in cfg_msicsr(0) to know whether I should send MSIs, is there a similar flag somewhere to find out whether legacy interrupts are enabled (probably corresponding to the "Interrupt Disable" flag in the PCI configuration space's command register).

 

Looking at altpcierd_tl_cfg_sample, the most likely candidate would be cfg_prmcsr(10).

 

It is a bit unclear how cfg_prmcsr maps to the control and status registers, especially as table 5-14 on page 5-34 of the PCIe hard IP user guide shows that signal as 16 bit wide, when it is implemented as 32 bits.

 

Since cfg_prmcsr(26) is hardwired to 0, my expectation would be that the command register lives in the lower bits, similar to how the control register in the PCIe capability structure maps to the lower bits of cfg_devcsr.

 

Can anyone deny or confirm that this is the bit to look at when deciding whether interrupts should be flagged by asserting app_int_sts, or should I just invert the MSI enable bit and trust the hard IP to filter out interrupts while they are disabled?

 

Is the width of cfg_prmcsr an error in the documentation?

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6 Replies
SengKok_L_Intel
Moderator
276 Views

Hi,

 

By referring to the user guide, the cfg_prmscr only provides the information of the PCIe status, but not the command register info. One suggestion is to refer to the cfg_msicsr[15:0] so that we can determine whether the MSI is enabled.

 

Regards -SK

SimonRichter
New Contributor I
276 Views

Yes, MSIs appear to work, and cfg_msicsr(0) tells me that they are enabled.

 

For the case where MSIs are not supported on the host, I'd have to fall back on legacy interrupts though. The documentation says that the host is allowed to switch between legacy and MSI interrupts by enabling one mechanism and disabling the other, so I would expect the host to disable legacy interrupts when it activates the MSI.

 

So now I'm wondering how that would appear to me inside the FPGA. I think I should be able to pick this up from cfg_prmcsr(10) going to '1', but I'd like some confirmation that this is a reliable method.

SengKok_L_Intel
Moderator
276 Views

Per the user guide, the cfg_prmcrs does not tell this is for the command register. If the MSI interrupt is enabled, the legacy interrupt must be disabled. I'm uncertain if the driver side can control to enable at least one interrupt (either MSI or Legacy interrupt) at any time, which means if the MSI interrupt is disabled, the legacy interrupt is supposed to enable.

 

Regards -SK

SimonRichter
New Contributor I
276 Views

Okay, so I'll assume that legacy interrupts are enabled if MSIs are not, thanks!

SengKok_L_Intel
Moderator
276 Views

Thank you for your understanding.

SengKok_L_Intel
Moderator
270 Views

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