Hi,
I am trying to send data between 2 dev boards (1 Intel Cyclone 5 Soc Kit and 1 Terasic Cyclone 5 GX starter kit) together using fiber optic SFP. Both dev boards have the terasic SFP daughter board attached to them via HSMC. I am running into an issue where the sync_sm mode for the RX word alignment mode parameter does not seem to function properly.
-I am using 8b/10b
-I am using 1 channel (1 fiber optic cable)
-Clock is being sent and is aligning properly
Whenever I send data using the custom phy native phy IP, it seems that the Rx side is locking onto the clock at random without performing any bit slip. Sometimes it syncs correctly sometimes it doesn't, which leads me to believe that the sync_sm mode is not cycling through the bits correctly.
According to a previous reply by an Intel employee: "As for state machine mode, it will perform auto alignment after XCVR coming out from reset. It will look for pre-defined word alignment pattern configured in Native PHY. " (https://community.intel.com/t5/Programmable-Devices/Will-the-receiver-auto-align/m-p/266156) I tried to manually reset the Custom Phy using the reset controller, but it still does not seem to sync with the pre-defined word pattern. It's as if the sync_sm function is not working at all. I could not find much info on how sync_sm operates. Can someone provide any clues as to what I am missng? Thanks.
