02-24-2012 07:54 AM
Hi, everyoneI am doing a SD-SDI transmitter on the Arria II Gx development kit. A test pattern and a clock video output are containned in my SOPC. (The resolution of test pattern and clock video output is 720*480. The parameter setting of the clock video output is loaded from NTSC) The clock video output is connected to a SD-SDI megacore IP to transmit the generated test pattern. When I use a capture card from StreamLabs and preview the video in VLC media player, I see a short horizontal green line in left bottom of the test pattern, as you can see in the attached picture. Does anyone have a clue about how this green line is shown? Is there any way to fix this problem? (The top model of my design is provided as the attached file.) Thanks. -Curtis
02-24-2012 08:56 AM
Thanks FvM for your reply.Since the test pattern is generated by an IP in Video and Image Processing (VIP) Suite MegaCore Functions, I thought that the test pattern should be correct and I didn't check it. I'm a beginner in Altera FPGA and have no idea about how to check if the green line is in the test pattern RAM image. Could you please tell me how to do it??? Thanks a lot. -Curtis
02-24-2012 02:03 PM
I believe the NTSC loaded by the clocked video output is 487 lines interlaced. Perhaps the short green line (7 pixels before the bottom?) is related to thatYou cannot generate 487i with the Altera TPG but there is a workaround suggested in the user guide: "The Test Pattern Generator cannot produce interlaced streams of pixel data with an odd frame height. To create interlaced video streams where F0 fields are one line higher than F1 fields, Altera recommends feeding Test Pattern Generator progressive video output into the Interlacer MegaCore function."
02-24-2012 03:45 PM
Hi, vgsAccording to your opinion and the VIP user guide, I will adopt progressive mode in my test pattern generator and test it again next week when I go back to my office. I will let you know if the problem is solved by this solution. Thanks.