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Altera_Forum
Honored Contributor I
1,159 Views

altclkctrl mux with 2 pll outputs as inputs

I have clk_a and clk_b from 2 pll outputs, and I want to mux them to clk_out with altclkctrl. but Q2 complaints that altclkctrl inputs " must be driven by 1 PLLs but is driven by 2 PLLs" . What can i do to fix it? Is there any other solution which without violating the C101 rule about gated clock?

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Altera_Forum
Honored Contributor I
50 Views

Another way of generating clk to output pins is the use of DDR out instant. set one input high, the other low , the dataout is your clk. additionally you can add clk enable as required. This allows for edge alignment as well. Data need not be DDR.

Altera_Forum
Honored Contributor I
50 Views

The problem is that I can't choose the way of generating the clks, I 've to use 2 PLLs at the moment. I've no choice but to figure out a way to mux 2 pll outputs. I am currently using "assign clk_out=clk_sel==0?clk_a:clk_b;" but that's violating the C101 rule.

Altera_Forum
Honored Contributor I
50 Views

try use one PLL and remember that gating rules apply to internal fpga clk use. If your clks are only for outside world then you can gate them and manage your timing accordingly.

Altera_Forum
Honored Contributor I
50 Views

If I violated rule C101 (using a simple 2:1 mux), what's the harm of doing this? the clock glitch?  

Is the glitch only happened on the switchover point? If so, can I avoid the glitch by sampling data several cycles after the switchover?
Altera_Forum
Honored Contributor I
50 Views

glitch at switch over is not an issue if your switching is occasional. The main problem with clk gating is clk skew(delay) leading to hold time violations. This applies to registers inside FPGA. If your clk is for outside registers then tackle timing according to your clk/data transition at pins and further. 

ASIC designers normally gate their clk and tackle timing accordingly.
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