Hi everyone,
i'm working on arria10 soc board and i try to display a video that comes from a gigabit ethernet link and a 640x512 24b (8 bits per pixels + 3 color planes) rgb custom camera. For the moment, i don't use DDR4 for image buffering.
Instead i use a huge 2 ports on-chip memory for test (1310720 bytes). ( slave0 -> ram to dma interface(clock 148.5 MHz), slave1 -> camera rgb pixel (clock 125MHz))
I have a state machine that writes pixel data to this RAM on slave1 side while there is a DMA (university program one, consecutive addressing) that reads (slave0) this RAM
The vip mixer has 2 input : 1) 640*512 test pattern generator color bars 2) DMA
In my C program, i start IPs in this order 1)cvo 2)mixer 3)test pattern 4)dma
For the moment, i can display the color bars but as soon as i start the DMA, it disappears and only back ground from mixer is shown.
My questions are :
1- do i have to write a st control packet to ram firstor it's generated by dma itself?
2- if yes, is this control frame sequence valid?
sof + data_to_stvideo <= x"00000" & "1111"
data_to_stvideo <= x"00" & Iwidth(7 downto 4) & Iwidth(11 downto 8) & Iwidth(15 downto 12)
data_to_stvideo <= x"00" & Iheight(11 downto 8) & Iheight(15 downto 12) & Iwidth(3 downto 0)
data_to_stvideo <= x"00" & Interlacing_nibble & Iheight(3 downto 0) & Iheight(7 downto 4)
2- I write pixel data to ram like this but i'm not 100% sure : data_to_ram(31 downto 24) <= (others => '0') and data_to_ram(23 downto 0) <= red&green&blue and i increment address on next pixel
thank you for anything that can help me
