calculatin of resource utilization by an IP core

[Altera_Forum]

Hello, 

I wanted to know how to calculate the resource utilization by an IP core for a target FPGA. For Eg, i have a requirement where in i need to use NIOS II/f core, TSEMAC(4 port) core, 4 PIOs, avalon on chip shared memory, SDRAm controller core, Flash controller core, EPCS device controller with avalon switch fabric interconnects. Now i need to know whether i can fit all these in single FPGA targetting cyclone II/III. I need to do this without compilation. The datasheets does not give any information about resource utilization for any peripherals(except TSEMAC).  For TSEMAC, the resource utilization is provided for cyclone III(FBGA) package , but i need to calculate it for TQFP/PQFP package. can i just take the percentage ratio and calculate? for eg: for cyclone III(EP3C120F78017) the LE's :15594, registers:10509, memory(M9K):41, fmax:>125MHz. with this can i calculate the same for cyclone III/II(PQFP/TQFP) device?  I have a urgent requirement. i hope for a fast reply ..   thanks,

[Altera_Forum]

There is no differences depending on package. The same resources will be required for the wired chips. Note: QFP packed chips as usual have slowest time gradation. Check that you use corresponding time: -5 or -6.

[Altera_Forum]

ok thank you...

[Altera_Forum]

hello, 

Some more help needed w.r.t speed grade.. How does speed grade effect the resource utilization? suppose, cyclone III(EP3C120F780I7-speed grade -7) device utilizes 15594 LE's and i need to find out resource utilization for EP3C40Q240C8, speed grade-8), what is the aspect i need to consider w.r.t speed grade.. And what is the difference between -5,-6,-7,-8 speed grades.. which is the fastest device among above?

[Altera_Forum]

smaller number speed grades are fastest, in this case -5. 

 resource usage should be the same per speed grade but i suppose it could vary slightly depending on constraints and physical synthesis options.