Hi,
I use the example created by Megafunction with my own controller to simulate my design because I use Web edition QuartusII 7.2. I initialize DDR2 SDRAM successfully. My problem is that in calibration process, the sequencer sends block of 8 consecutive write requests and then repeatly sends blocks of only 8 consecutive read requests to controller,instead of 9. After some time, the "local_usr_mode_rdy" is high, it means I can write, read data normally. But in normal process, I see that the read data (local_rdata) and their valid signal(local_rdata_valid) sent to controller are not correct, exactly, the valid signal is delayed many clock cycles to data. If I delay the valid signal, read data and valid signal is okay. Do you think there is any wrong or unusual?
I need your help very much!
Tuan,
