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5890 Discussions

custom component with DCFIFO

Altera_Forum
Honored Contributor II
759 Views

Dear nios user! 

 

I had associated a custom component(with DCFIFO) to Nios2 system. I used avalon MM slave interface and conduit interface. 

 

My custom component is 

 

module fifo_in ( 

// Avalon clock interface siganals 

input csi_clockreset_clk, 

input csi_clockreset_reset_n, 

// Signals for Avalon-MM slave port 

input avs_s1_address, 

input avs_s1_chipselect, 

input avs_s1_read, 

output [31:0] avs_s1_readdata, 

input avs_s1_write, 

input [31:0] avs_s1_writedata, 

// Signals export to top module 

input avs_s1_export_clk, 

input avs_s1_export_req, 

input [31:0] avs_s1_export_capture_readdata 

); 

fifo_32 u1( 

//read side 

.q(avs_s1_readdata), 

.rdclk(~csi_clockreset_clk), 

.rdreq(avs_s1_read), 

 

//write side 

.data(avs_s1_writedata), 

.wrclk(~csi_clockreset_clk), 

.wrreq(avs_s1_write) 

); 

endmodule 

 

My Source Code is 

 

for(i=0; i<0x10; i++) 

IOWR(FIFO_IN_0_BASE, 0, i); 

 

for(i=0; i<0x10; i++) 

printf("0x%08x ", IORD(FIFO_IN_0_BASE, 0)); 

 

This is FIFO read and write is OK. 

 

But, my custom component is modified. Modified custom component is 

 

module fifo_in ( 

// Avalon clock interface siganals 

input csi_clockreset_clk, 

input csi_clockreset_reset_n, 

// Signals for Avalon-MM slave port 

input avs_s1_address, 

input avs_s1_chipselect, 

input avs_s1_read, 

output [31:0] avs_s1_readdata, 

input avs_s1_write, 

input [31:0] avs_s1_writedata, 

// Signals export to top module 

input avs_s1_export_clk, 

input avs_s1_export_req, 

input [31:0] avs_s1_export_capture_readdata 

); 

fifo_32 u1( 

//read side 

.q(avs_s1_readdata), 

.rdclk(~csi_clockreset_clk), 

.rdreq(avs_s1_read), 

 

//write side 

.data(avs_s1_export_capture_readdata), 

.wrclk(avs_s1_export_clk), 

.wrreq(avs_s1_export_req)  

); 

endmodule 

 

Modified custom component's read value is  

0x00000000 

0x00000000 

0x00000000 

0x00000000 

.... 

 

Please help me. Thank you.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
67 Views

I have tested input data that is camera signal. 

avs_s1_export_capture_readdata is camera's image data. 

avs_s1_export_clk is camera's PIXCLK. 

avs_s1_export_req is camera's HSYNC and VSYNC. 

 

I get exactly above signal(camera image data, PIXCLK, HSYNC, VSYNC). 

 

What is wrong? 

Please help me...
Reply