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Valued Contributor III
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ddr2 sdram

Hello, I'am new to SOPC build,and sorry for my poor english. 

I have bought a dsp development kits from alter,and there is an ddr2 sdram on this development board. 

this is the development kits I have bought: 

http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-1699-nd 

In my sopc build, i only add there components: niso ii cpu,jtag uart and ddr2 sdram controller megacore funtion - altera corporation 

I don't know how to fill these parameters about this ddr2 sdram controller,when i generate this cpu by default setting,I found there are some files about pll(such as ddr_pll_cyclonii) are generate by system,I don't konw how to use these files. 

can anyone help me,or send me a example about,thank you 

adream307@gmail.com
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Valued Contributor III
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these parameters refer to timing parameters for the DDR2 you actually have in your kit. so you have to read the corresponding data sheet of the DDR2 and fill in the blanks! 

I recommend to take the "standard" design as a starting point.
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Valued Contributor III
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--- Quote Start ---  

these parameters refer to timing parameters for the DDR2 you actually have in your kit. so you have to read the corresponding data sheet of the DDR2 and fill in the blanks! 

I recommend to take the "standard" design as a starting point. 

--- Quote End ---  

 

 

Thank you for your reply. 

I find that the "standard" project is built in Quartus5,but I am using Quartus9. 

I build a simplest project, it only contain Nios II CPU + jtag uart + ddr2 sdram, and fill the dd2 sdram's parameters as the "standard" dose. 

But I get this error message when I compile my project: 

 

Following DDIO Output nodes could not be placed by the Fitter 

 

Now I don't know how to deal with this error 

 

adream307@gmail.com
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Valued Contributor III
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I am happy to tell you that I am using the same board that you have! 

Anyway, to deal with old versions you would only open the SOPC Builder and chose to upgrade the design and then continue using your version normally. 

Tell me what assignment did you use for the DDR2 pins? I think that you assigned them using the ep2c70f672 board location while you must use the original ddr2 core location (Refers to the reference manual of the board.) 

I again recommend to use the standard design which comes with the board documents (<..>\Kits\CycloneII_DSP_Kit-v6.0.1\Examples\NiosII\example_designs\verilog). The design has its correct assignment and any other parametrization.
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Valued Contributor III
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--- Quote Start ---  

I am happy to tell you that I am using the same board that you have! 

Anyway, to deal with old versions you would only open the SOPC Builder and chose to upgrade the design and then continue using your version normally. 

Tell me what assignment did you use for the DDR2 pins? I think that you assigned them using the ep2c70f672 board location while you must use the original ddr2 core location (Refers to the reference manual of the board.) 

I again recommend to use the standard design which comes with the board documents (<..>\Kits\CycloneII_DSP_Kit-v6.0.1\Examples\NiosII\example_designs\verilog). The design has its correct assignment and any other parametrization. 

--- Quote End ---  

 

 

Thank you very much ^_^ 

I surprise to find that I can build the "standard" project after upgrade,and I can run the "hello world" program in "standard". 

Then I remove unused components,the only left components are cpu, epcs controller,jtag,on chip memory and ddr2 sdram. 

After these actions, I rebuild the "standard",I find that "hello world" program can still run on this cutted "standard". 

Now I create a project , it contain cpu,epcs controller,jtag,on chip memory and ddr2 sdram,all the parameters is same as the "standard",and write an top module using verilog language not by a .bdf file. 

I can compile my project successfully,but when I run "hello world" program on this cpu,I get this information: 

Verifying 04000000 ( 0%) 

Verify failed between address 0x4000000 and 0x400E243 

Leaving target processor paused 

 

Thank you:)
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Valued Contributor III
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I am glad to know that I could give help. 

I don't exactly know why that error occurs, anyway you should not leave the standard design and just apply your modifications on it cause the project has its own constrains (refer to Assignments > Assignment Editor > Categories > Timing.) 

good luck
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Valued Contributor III
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--- Quote Start ---  

I am glad to know that I could give help. 

I don't exactly know why that error occurs, anyway you should not leave the standard design and just apply your modifications on it cause the project has its own constrains (refer to Assignments > Assignment Editor > Categories > Timing.) 

good luck 

--- Quote End ---  

 

 

I am happy to tell you that I have solved my problem. 

The clock for ddr2 sdram controller has 0 degree phase,but the clock for ddr2 sdram write has -90 degree
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Valued Contributor III
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are you using the DDR2 with it's full scale (256 MB)?

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Valued Contributor III
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--- Quote Start ---  

are you using the DDR2 with it's full scale (256 MB)? 

--- Quote End ---  

 

 

No, In my project, all the parameters are the same as "standar",so the memory data bus width is 16. 

But when I change the memory data bus width to 64,I confront the same error message: 

Following DDIO Output nodes could not be placed by the Fitter 

 

When I assign my pins as you advised, I still get this error.
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Valued Contributor III
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I could raise the memory size to 128MB, and there was no error like what you said, maybe you should re-assure the assignments! 

Anyway I am stuck with using the full size which is 256MB, the memtest fails there.
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Valued Contributor III
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--- Quote Start ---  

I could raise the memory size to 128MB, and there was no error like what you said, maybe you should re-assure the assignments! 

Anyway I am stuck with using the full size which is 256MB, the memtest fails there. 

--- Quote End ---  

 

 

When setting the parameters of ddr2 sdram controller in sopc build, I don't know how to deal with "constraints",I don't what's "constraints" mean? 

 

Thank you
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Valued Contributor III
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I think it's the way you locate the DDR2 controller on-chip and that is often used to meet some critical path requirements. Keep it as the default.

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Valued Contributor III
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--- Quote Start ---  

I think it's the way you locate the DDR2 controller on-chip and that is often used to meet some critical path requirements. Keep it as the default. 

--- Quote End ---  

 

 

May I have your email? 

Thank you! 

In my project, I set "memory data width" to 64,and let all others the same  

as the "standard" project,and assign my pins following the original ddr2  

core location 

But I get this error information when I run "Hello world!" 

 

Verifying 10010000 ( 0%) 

Verify failed between address 0x10010000 and 0x1001001F 

Leaving target processor paused 

 

Thank you
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Valued Contributor III
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something goes wrong when using the full data width for the DDR2  

 

mhd.mayya@gmail.com
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Valued Contributor III
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--- Quote Start ---  

something goes wrong when using the full data width for the DDR2  

 

mhd.mayya@gmail.com 

--- Quote End ---  

 

 

Do you raise your ddr2 sdram's memory by change "memory data bus width" or change the "chip select"? 

I found that when I set "memory data bus width" to 32,and let "chip select" to be 1, I can use 128M of the ddr2 sdram.But when I set "chip select" to be 2 or change "memory data bus width" to 64,they both don't work well. 

I found another phenomenon, quartus9 will assign "dq,dqs,dm" automatically,and you must use these automatically assigned pins,otherwise you will get a "DDIO" error when compile these project.
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Valued Contributor III
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First of all you can not use 2 chip select cause the DDR2 you are using doesn't support two chip select. 

Second, the automatic assignment you are talking about are pre-assigned since you are using the "standard" template. 

Finally, I am having the same problem when I am trying to increase the data width to 64-bit, it's something I cannot figure out!
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Valued Contributor III
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--- Quote Start ---  

First of all you can not use 2 chip select cause the DDR2 you are using doesn't support two chip select. 

Second, the automatic assignment you are talking about are pre-assigned since you are using the "standard" template. 

Finally, I am having the same problem when I am trying to increase the data width to 64-bit, it's something I cannot figure out! 

--- Quote End ---  

 

 

Thank you! 

I build a new project, it only contain cput, jtag uart and ddr2 sdram, I am not using the "standard" template.but the quartus still automatic assigg the pins. If quartus didn't assign the pins automatically,and I finish the pins assigment manually, I will get an warning in "Filtter" process,the waring is something about "capacitance",and I can compile this project succefully,but I can't run "hello world" on it.
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Valued Contributor III
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anybody knows how to sotore data in SDRAM using DSP builder? 

thanks!!
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