direct instantiation of altera_mf_components IP from VHDL

[timeportal]

When moving up from Intel/Altera 17 to 22 I am noticing a trend that maybe  instantiation of altera_mf_components IP directly from within VHDL is no-longer supported, or will be supported in the future for only a very limited set of IP. This type of VHDL direct instantiation was used in many of my libraries in the past so that I could use VHDL generics to control for example the widths of various ports.

The overarching policy for such things at Intel/Altera is maybe somewhat mixed/confusing. For example, I see that component altsyncram exists in "quartus//libraries/vhdl/altera_mf/altera_mf_components.vhd", and the design compiles in quartus. However, when I run the simulator I see a message like below, and I discover that an interface called altera_syncram is not in "quartus//libraries/vhdl/altera_mf/altera_mf_components.vhd."

Error: Error: altsyncram vhdl simulation model is deprecated for Stratix 10 onwards family. Instantiate altera_syncram for vhdl simulation.

It is possible to fix such problems by instantiating the IP from a TCL script, but it requires substantial effort to rework all of my libraries.

Should I assume that Intel/Altera will be dropping support for VHDL direct instantiation of  altera_mf_components as a preconceived, coordinated, and deliberate policy in the future?

Thanks

[KennyTan_Altera]

Altera is shifting away from using direct VHDL instantiation for certain IP cores, especially in its newer FPGA families like Stratix 10. Instead, the focus is moving toward using tools such as Platform Designer and TCL scripts. This change helps standardize how IP cores are integrated into projects and unlocks access to advanced features that aren’t available through the older VHDL method. It also improves simulation workflows and integrates more smoothly with Altera development tools.

To keep up with these changes, IP cores must be updated within Quartus to ensure they're compatible with the latest FPGA features. As direct VHDL support becomes increasingly limited, it's a good idea to start converting your existing design libraries to the newer, tool-based approaches. Begin with the libraries most impacted by the changes.

[timeportal]

From my perspective, the use of VHDL generics for configuring the IP is actually the more modern, and not an older, approach for configuring device specific an d or proprietary features, and is more tightly integrated with HDL. Use of GUI tools is certainly easier for beginners. but the heavy lifting is  actually done in text based HDL. Likewise, only from my perspective, TCL is an outdated and archaic language.

[FvM]

As far as I understand, existing libraries like altera_mf are not removed, but they are not available to map the hardware of newer FPGA series, e.g. Stratix 10. This is primarily due to the complexity of these devices, not because someone considers the interface method as antiquated.

I remember when moving from altpll to altera_pll IP with Cyclone V, it was effectively impossible due to increased complexity to configure it according to IP user guide, you needed to generate the configuration by Megawizard and copy it to your HDL.

[KennyTan_Altera]

When Quartus is updated, you often need to change your HDL files to fix bugs and add new features. This happens because FPGA technology and IP settings keep getting better. While HDL lets you control details, it can be hard to manually update everything each time. GUI tools like Megawizard in Quartus make it easier by automatically applying updates and changes to your IP settings. This ensures your designs work well with the latest upgrades without having to rewrite everything yourself. Using GUI tools with HDL helps keep your projects compatible and up-to-date efficiently.

[KennyTan_Altera]

Do you have further or more question? If no, we shall close this thread.

[KennyTan_Altera]

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