FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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displayport quad pixel mode

Honored Contributor II

Hi everyone, 


i want to display a 2k video from a test pattern genarator module in to a display using display port. while configuring display port TX-pixel input mode to quad i found that 4 Hync 4 Vsync and 4 De signals are needed as input..but i have only one de hsync vsync signal from from my pattern generator. . my question is why there are 4 hsync 4 vsync and 4 de signal if i select quad pixel at display port tx input ? if my input is 4 pixels a clock why a single hsync vsync and de signals are not suffitient?
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Honored Contributor II

if you configure display port TX-pixel input mode to quad, then, tx_vid_clk is a quarter of pixel clock.so you can give low clock but run high pixel clock, that is the purpose of this setting.