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Altera_Forum
Honored Contributor I
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dummy component

Hi,  

I have an SOPC system, in which the nios processor writes to a fifo. I would like to create a customized component: FSM, to read the fifo, scramble the data then write to the LVDS transmitter.  

 

Q1: The FSM with an Avalon-MM read master interface, but how can it accesses fifo's SCR registers, given a dual-clock fifo? 

 

Q2: I have a dual clock fifo symbol, with input data[31..0], wrreq, wrclk, wrfull, and other output signals. I tried to make a dummy component to wire those input up outside SOPC. The template of Avalone-MM Slave with Interrupt is used. (2.1) Why cannot I remove the read associated signals e.g. read, readdata, readdatavalid? (2.2) Should I include a conduit with four signals, e.g. data_o, wrreq_o, wrclk_o, and wrfull_i, export them in interface. and connect them in the verilog? Any suggestion? 

 

Thanks.
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