FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6228 Discussions

error simulating 10GbE MAC IP

Honored Contributor II



I am trying to simulate 10GbE MAC IP. I am using Megawizard mode and write my own avalon-mm master to communicate to the IP.  

I am using Quartus II 11.0/11.1. I got the following error while trying to simulate my 10GbE IP based design.  

# ** Error: (vlog-7) Failed to open design unit file "C:/FPGA_work/example_design_v11_0/eth_10g.vo" in read mode.# No such file or directory. (errno = ENOENT)# ** Error: C:/altera/10.0/modelsim_ase/win32aloem/vlog failed.# Error in macro ./example_design_v11_0_run_msim_rtl_verilog.do line 8 


How to generate .vo file using Quartus, I believe this file is automatically generated, as in TSE IP when we select to generate simulation model but there is no such parameter in this IP? 


How to do simulation with 10GbE MAC IP design? 



0 Kudos
0 Replies