fircompiler becomes less efficient?

[Altera_Forum]

Hello friends, here's my story. 

last week. FIR filter designed using Altera fircompiler with Quartus II v8.0 sp1 for the Cyclone III starter kit board, the one with the '3C25 chip. 70 14-bit taps and 16-bit input, rectangular window. The result was 3089 LEs, directly readable from the fircompiler design window. today. Exactly the same filter, but with Quartus II v8.1. This time 5474 LEs. I really don't understand this. Is it a simple way to lead customers towards larger FPGAs? Have you experienced this kind of growth? Cheers. OD

[Altera_Forum]

When opening the V8.0 project, I think, Quartus V8.1 informs you that default settings have been changed. Some may be inappropriate for your application.

[Altera_Forum]

Hello 

 I've had the same problem here. Try compiling the design in both versions. You should see that the FIR size is actually different from the prediction on the design window. The new version size should be more or less the same as the old one  Regards,  Thiago

[Altera_Forum]

Yeah, thank you Thiago. Indeed there is a very slight change in the real size of the filter after compilation. 

It's always good to know the defects of our working tools...  Cheers. OD