Can you share more information?
Version of tools and Full name of the IP used in you design with simulation images.
If possible do share project files.
am using 18.1 quartus tool and IP name is "ESRAM" here am attaching the project files and the simulation waveform capture,while generating the IP core i configured the 'refclk' as 100Mhz and output clk as 500Mhz but when am trying to drive the reflck from the testbbench am able to get the refernce clk but am unable to generate the output core clk and lock signal , is there anything i have to drive from the testbench??