integration of DSP Builder model in Quartus

[Altera_Forum]

I've designed a simple logic design in DSP Builder, basically reading and writing some I/O ports, after compilation and downloading it works fine running in a Cyclone III. 

 I want to integrate it in a complete NIOS System, using tcl scripts I've included this new model in the SOPC Builder library but It cannot be added (I think because it hasn´t an Avalon Interface).  How can I integrate this model in Quartus? Do I need use .vhd file? In this case How can I do it to integrate in a schematic design?

[Altera_Forum]

in your Signal Compiler block go to the Export HDL tab and click the button. in your Quartus project add the generated .qip file to your project. there will be a .vhd file with the same name as your .qip and .mdl that you can interface to your DSP Builder system with.

[Altera_Forum]

Thanks for your explanation, 

 I've Exported the DSP builder model to HDL from Signal Compiler.  My top level file includes a system developped in SOPC builder (NIOS + Memory + Ethernet)  Can you tell How Exactly how can I included the hdl file to the project.  I don't know How I can do an schematic block with HDL file.  Thanks in advance

[Altera_Forum]

so your top level is a .bdf schematic file? 

 you can create a .bsf symbol file for any HDL file by going to the Project Navigator then Files tab, right clicking on the .vhd, and choosing Create Symbol Files for Current file.

[Altera_Forum]

Thanks a lot for your great help. The vhd block is working now in parallel with the rest of the system. 

 Now I'm thinking on to send incoming data (input ports) to memory within the memory of the NIOS system by using an MM-Avalon port using a DMA controller.  What would be the best way to do it?  I would be Using tcl scripts and selecting the block from the library in SOPC Builder?