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issue in SOPC: the PLL of the DDR2 HighPerformanceController cannot be synthesized

Honored Contributor II

At the moment i try to set up a testsystem for my project. I found an example wich do exactly what i need for a testsystem at nioswiki.com/exampledesigns/nios2udpoffloadexample. I use the Stratix-II-gx-pci-devkit board, the example is designed for that board. 

Unfortunately if i start the run script it throws an error at the generation of the sopc builder system. If I open the project manually and start the sopc builder, i can see the following message at the messages window: 


Error: ddr_ram: the given combination of pll input and output cannot be synthesized 


It occures everytime I add the DDR2 SDRAM High Performance Controller to any kind of system. I try it in Quartus II 9.1sp2 (same version MegaCore-IP-Library) and at Quartus II 10.0sp1 (same version MegaCore IP-Library). I found an hint at the Errata sheet of the MC-lib (altera.com/literature/rn/rn_ip_91.pdf). I dont use cyclon IV E device like mentioned there, but the stratix II gx device. At this board there is the max speedgrade 5. I poke around the Parameters in the mega-Core, and the manuals but don't find an solution. 

Do any of you encounter the same problem, and how can i solve/work around it ? 


best regards 


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Honored Contributor II

seems to be fixed in 10.1sp1. At version 9.1sp2 - 10.0 this example doesnt work on this board

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