issuing memory write request from PCI Express endpoint

[Altera_Forum]

Hi! 

 I'm trying to send data from my PCI Express endpoint (StratixIV Hard IP) to the root port memory. For that I would need the enpoints device ID (to put it in the requester ID field of the header). Unfortunately there seems to be no register in the configuration space that holds this information. Now to get the device ID I sent a configuration read/write request from the driver (Jungo WinDriver) to the device as this should contain the ID (in the completer ID field of the header). Unfortunately I never receive any configuration request on my device although I can successfully communicate via the PCIe link (e.g. memory write request from root port to endpoint). It seems like the configuration requests are handled by the hard IP itself, and are not passed to the user application.  How can I determine my device ID (bus nr., device nr., function nr.) from my PCI Express endpoint:confused:

[Altera_Forum]

You can use the tl_cfg_xx signals. Look at section 5-31 (Configuration Space Signals - Hard IP Implementation) in the PCI Express User Guide. I'm using these to capture the requester ID in an Arria II GX hard macro design. The tl_cfg_ctl_wr signal toggles high/low every 8 ticks, and you just need to use both edges as a qualifier to know when to sample the tl_cfg_add tl_cfg_ctl. The information you need is at address 0xf.

[Altera_Forum]

thanks, it seems I've overread this. Is there a detailed description of the cfg_busdev register somewhere? 

Maybe I will try to capture the value and then I will see...

[Altera_Forum]

Practically you don’t have to care about the contents of cfg_busdev unless you are a root port or you implement multiple functions. Just use it whenever sending a TLP. If you want to know more about cfd_busdev, look into the PCIe Specification, Section labelled »Transaction Descriptor – Transaction ID Field«. The 8 MS bits are the PCI Bus Number, then there are 5 bits Device Number, and the 3 LSBs are the Function Number.