FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5886 Discussions

jtag uart reading and parameters

Altera_Forum
Honored Contributor II
793 Views

Hello all, 

do you have some experiences with setting Altera logging options, which are meantioned on page 6-11, 6-12 in Nios II Software Developers Handbook ? I mean the ALT_LOG_JTAG_UART_TICKS - default is 10 (ticks per second). Or HW FIFO wspace = 64. Where am i able to set these values ? 

When we use in linux terminal some command like this: 

\> cat file.hex > nios2-terminal 

 

and i have some design and program which read jtag uart and sending on the leds, i saw on oscilloscope that i am able to read only 64 bytes per 100ms (its determinated i think these parameters ALT_LOG_JTAG_UART_TICKS and HW FIFO wspace = 64) and it is too small for my application. 

 

Thank you for your answer. 

 

Jan Naceradsky, Czech Republic
0 Kudos
0 Replies
Reply