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Altera_Forum
Honored Contributor I
992 Views

max burst size

Can you tell me why the max burst size for Altera DDR2 DRAM is set at 64? 

I need to transfer 1.2Mb of data in more than 64 64 bit blocks (4096 bytes)
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Altera_Forum
Honored Contributor I
53 Views

Please explain what you mean by this statement: "I need to transfer 1.2Mb of data in more than 64 64 bit blocks (4096 bytes)" 

 

At the DDR2 device level the burst size is either 4 or 8, so it's very nice that the Altera controller allows you to use bigger bursts on the user side, which the controller then breaks down into many smaller bursts of 4 or 8 on the memory side. I assume that the choice of 64 as the maximum was just a somewhat arbitrary design choice. They had to pick something as the maximum and they happened to choose 64. 

 

What is the problem with breaking your transfer into as many bursts of 64 as needed to complete it?
Altera_Forum
Honored Contributor I
53 Views

 

--- Quote Start ---  

Please explain what you mean by this statement: "I need to transfer 1.2Mb of data in more than 64 64 bit blocks (4096 bytes)" 

 

At the DDR2 device level the burst size is either 4 or 8, so it's very nice that the Altera controller allows you to use bigger bursts on the user side, which the controller then breaks down into many smaller bursts of 4 or 8 on the memory side. I assume that the choice of 64 as the maximum was just a somewhat arbitrary design choice. They had to pick something as the maximum and they happened to choose 64. 

 

What is the problem with breaking your transfer into as many bursts of 64 as needed to complete it? 

--- Quote End ---  

 

 

Time constraints we need to transfer live HD video into the FPGA, between 1 and 2 Mb each image.
Altera_Forum
Honored Contributor I
53 Views

Hello, 

Description: I’m working under a project, which includes my custom IP to communicate over the Avalon-MM interface with NIOS-II /f. My custom IP is structural design and contains following components: Avalon-MM Slave bus, custom single dual-port block memory (separate writes and reads, and set for M10K). The writes supposed to transfer 32-bit data to the 24-bit single clock dual-port block RAM from the NIOS by software, and reads from an external device, such as our custom VGA controller. The custom Avalon-MM implemented in VHDL and has following ports: ADDRESS, CHIP SELECT, BURST COUNT, WRITE DATA, WRITE, READ DATA, READ, WAIT REQUEST, RESPONSE and READ DATA VALID. The VGA Controller just simply reads the data from the block RAM (no Avalon interface). The FPGA target is Cyclone-V, device: 5CSEMA5F31C6; Quartus II Subscription Edition v 15.0; Windows 7. 

Question 1: How the software infers the burst counts over the Avalon-MM interface? I assume, it could be by “for’ or “while” loops in C code. Is that correct? Of course, the custom component and the NIOS have to support burst count modes. This is the one approach I can implement my design to write data into the single clock dual-port block RAM. 

Question 2: Is it worth to implement the writes into the RAM is to create the second Avalon-MM interface such as CSR (Control and Status Register), similar to the DMA or SGDMA? That would include destination address, data length, control and status registers with certain address offsets.  

Question 3: Where I can get the Avalon-MM Slave bus template? Altera wiki doesn’t work for me, there are Verilog-based design and it contains a lot of unnecessary info. I need VHDL. 

Question 4: What would you recommend in my case? Approach described in question 1 or 2? 

Kind Regards, 

Val
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