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Altera_Forum
Honored Contributor I
1,334 Views

min max frequency requirement of altera IP components

Hi all, 

 

I have modified the standard project provided by the cycloneIII_3c120_embedded so that some of the components work at a lower frequency. Unfortunately while the project synthesizes without any problem the simple hello world program does not give the output in the console and neither does the systemid component seem to work. 

 

 

In the unmodified project : CPU is driven at 100Mhz and systemid , JTAG UART, performance counter core are driven at 60Mhz ( using a bridge ) 

 

I reduced the system such that : CPU is driven at 50Mhz and systemid, JTAG UART , performance counter core are driven at 50 Mhz 

 

In both cases there is not timing violation. I have gone through some of the documentation for these IP's but could not find any max frequency spec. for the CPU i think there is a min frequency spec as well. Anyway i would like to know where i can find the min max frequency specs for the IP's of altera.  

 

Any help /suggestions are most appreciated 

 

Thanks
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3 Replies
Altera_Forum
Honored Contributor I
67 Views

Hi Silva, 

 

you can find a table for the CPU frequency at page two of this document: 

 

http://www.altera.com/literature/ds/ds_nios2_perf.pdf 

 

Generally the frequency is depending from your FPGA and the specific NIOS2 IP-Core too!
Altera_Forum
Honored Contributor I
67 Views

The table JacoL suggested should be considered only a reference for performance, I'd say an asyntotic upper limit. 

There are a lot of factors affecting the 'real' fmax you can attain. 

Mainly: 

- how much fpga resources are used 

- how much resources are available for routing 

- how much you are smart in placing timing constraints 

For example, I've been told (and I've quite verified it) that on a Cyclone III device you can't expect to safely use Nios/f core at a frequency above 100-120 MHz, unless your fpga is almost empty and you thoroughly check the timings after every recompilation. 

 

Regarding the lower frequency limits I don't know. I think this depends from pll minimum operating frequency.
Altera_Forum
Honored Contributor I
67 Views

Hi again, 

 

Cris is very right here. I tested to raise up the frequency of the CPU on a Cyclone III to 150MHz and failed. The 120MHz is a good value for the Cyclone III. A lot of the possible performance on the NIOS2 depends also on the points Cris noted for you! 

Sorry I forgot that point while I searched the table, thank you Cris!
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