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Hello,
I'm having a problem with using interrupt within msgDMA.
I'm using MAX10 development kit.
The design includes msgDMA (ST to MM) which transfers data from FIFO (Avalon-ST Dual Clock FIFO Core) to on-chip memory (On-chip RAM) and apply an interrupt when transfer completes.
However, the IRQ signal remains at level '1', and the only way I managed to lower the signal (reuse the interrupt) was by resetting the dispatcher of the msgDMA (and the reset process takes some time).
Is there another way to relaunch the interrupt of the msgDMA? i.e a way for the system to succeed catch the next event.
Thanks,
Lior
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Please allow me some time to check on this.
Could you help to share the design? or screenshot on the behavior that you are currently seeing?
Best Regards,
Richard Tan
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Please may checkout this user guide on the recommended software flow to setup the descriptor and configuring the mSGDMA.
You may also checkout the blog written by other party.
Best Regards,
Richard Tan
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May I know does my latest reply helps to answer your question?
Best Regards,
Richard Tan
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Hello Richard,
Thank you for your help.
your reply helped me!
I managed to clear this bit by writing '1' to it.
Best Regards,
Lior
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

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