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Altera_Forum
Honored Contributor I
741 Views

multiple xaui interfaces

Does anyone have a suggestion for telling quartus that multiple xaui interfaces (using the A2GX hard xaui ip) all receive a refclk from the same clock, and thus all the xgmii_rx/tx_clk signals should be the same? There are tx/rx phase fifos in the IP block, so I would think I should be able to take advantage of those, instead of having my own external fifos and wasting logic and excess global clocks. I have 4 xaui interfaces, and I'd like to have the rx/tx sides all be referenced to one clock domain. I tried to use the altgx megafunction instead of the xaui ip, and feed the coreclkout signal from one block into the rx/tx_coreclk inputs on the other blocks with the 0ppm assignment set, but quartus gave me errors - it expected the rx/tx clocks to be fed by the local coreclkout, not by the coreclkout from an adjacent core, since the channels were bonded/used the rate matcher. 

 

Thanks!
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6 Replies
Altera_Forum
Honored Contributor I
45 Views

Forgot to add: I do realize the xaui phy ip core does have a xgmii_tx_clk input port, but if I feed it with a clock that is not it's own xgmii_rx_clk, I get timing violations with the core's internal reset. 

 

Thanks
Altera_Forum
Honored Contributor I
45 Views

Hello cronus10, 

 

if possible, could you please share your project with me? I'm trying to use the two available SFP+ interfaces from the Terasic's DUAL XAUI TO SFP+ HSMC BOARD by instantiating two "10 GbE Design Example" Modules on Qsys and connecting the respective XAUI lanes to different lanes on the HSMC A Port, but fitter give me some errors (Could not place auto-promoted clock driver), leading me to think that i'm missing something... If you could please give me some help would be of great kind. 

 

Thank you!
Altera_Forum
Honored Contributor I
45 Views

Forgot to mention: I'm using a Stratix V GX Development Board.

Altera_Forum
Honored Contributor I
45 Views

Sorry for the wait, I was out of the office for a few weeks. I was using the XAUI hard PCS on an Arria II GX, so it might be a little different (haven't done anything with any of the V series parts). 

 

I can't share much of the project, but for clocking I feed the recovered rx clock into the tx clock, and the board's refclk input into the pll_ref_clk input, and feed in a low speed phy management clock, with the proper transceiver reset controller. 

 

Good luck
Altera_Forum
Honored Contributor I
45 Views

Thanks for the reply. 

 

For now, I'll stick on using only one channel of the board. 

 

About the magic numbers, I was wrong about not using it when there is no loopback. It is necessary anyway. 

 

 

--- Quote Start ---  

Sorry for the wait, I was out of the office for a few weeks. I was using the XAUI hard PCS on an Arria II GX, so it might be a little different (haven't done anything with any of the V series parts). 

 

I can't share much of the project, but for clocking I feed the recovered rx clock into the tx clock, and the board's refclk input into the pll_ref_clk input, and feed in a low speed phy management clock, with the proper transceiver reset controller. 

 

Good luck 

--- Quote End ---  

Altera_Forum
Honored Contributor I
45 Views

Oh sorry, I think I misunderstood the question. So you've always been able to get the design working with one of the xaui interface, but you run into problems when you have two or more interfaces? Are they running off the same refclk? You will need to dump both into their own dual clock fifos, but then you read out of them (or write to them) with a common clock from one of the xaui interfaces (after letting them fill up a couple cycles to account for any phase difference). That being said, I'm not familiar with the Stratix V and XAUI soft IP. Depending on your design, you could also keep them on their own separate clock domains. 

 

Cheers
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