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Altera_Forum
Honored Contributor I
843 Views

question about ALTLVDS

I have 2 questions about the altlvds megacore when i use cyclone III to build my backplane system that i have one central control board,4 function boards,all of them plus on the backplane.the central control board communicates with the other function boards using lvds through backplane,the questions is: 

1 if i use cyclone III lvds pin,how long it can drive? should i use another lvds buffer to drive lvds signal.(the lvds signal coming from central control board ,and go through backplane to the function boards. 

2 the central control board sends clk ( lvds signal) to others boards,so all of boards use the same clk.but i am not sure that the clk and altlvds signal each function board received are phase align.Is the altlvds core working correctly when the input clk and data are source synchronism but not phase align?what should i do.
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3 Replies
Altera_Forum
Honored Contributor I
27 Views

Please supply more details on your LVDS bus. 

 

1) Are the control board to peripheral connections point-to-point? 

 

If so, and the links are unidirectional, then the protocol is standard LVDS. The Cyclone III device will work fine. 

 

2) If the bus is a multi-drop LVDS (M-LVDS), then you will need to check how things are terminated (on the backplane), and whether the Cyclone III device can drive enough current over the backplane.  

 

LVDS drives 3.5mA into 100-Ohms to create a 350mV signal. M-LVDS terminates the bus at either end of the bus with on the order of 100-Ohms (it might be different if simulations showed it would provide a better termination), so the pair of terminations look like a 50-Ohm load. The 3.5mA then generates only 350mV/2 = 175mV. This might not be enough for the receivers to work (usually it is). If Cyclone III can support M-LVDS (read the data book), then you should be able to boost the LVDS driver output current. 

 

3) If the bus is bidirectional, or LVDS drivers need to be tri-stated, then you might be in trouble with the FPGA. The Stratix II parts cannot disable their LVDS drivers. You will need to check whether the Cyclone III devices have the same (stupid) feature. 

 

National Semiconductor has lots of external transceivers that can be tri-stated, so you can use those attached to regular single-ended I/O pins (depending on I/O rate required for your application). 

 

As for clocking, it depends on timing. If you can change/reconfigure the designs of the control and peripheral board, then you can design the master to launch the signals with the required timing. If the peripherals use a PLL, then you can change the PLL phase to capture data. You can configure the ALTLVDS component with an external PLL, and then use the ALTPLL_RECONFIG component to step the LVDS receiver clock phase. You can use that to perform an eye-sweep of the data, and then adjust the clock to the optimal location. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
27 Views

the central control board communicates with each other boards use point-to-point lvds signal,not m-lvds,unidirection, using one to send data and the another to receive data.  

1 how long the lvds signal can walk through on backplane. 

2 if I adjust phase using PLL,it means that I must confirm what the phase relationship between the clk and data signal for each function sub board using instrument,that result in each function board has diffrent programme.Is there any other solution.
Altera_Forum
Honored Contributor I
27 Views

What frequency do the LVDS signals operate at? 

 

Assuming the signals are routed differentially, and the impedance of the boards and backplane does not generate reflections, the LVDS will have no issue running up to 100MHz+. I use 250Mbps LVDS over VHDCI cables that are 4ft long (using Stratix II FPGAs). If your backplane is shorter than 4ft, you will be ok. Longer than that, and you will need to check things work. 

 

If the control board sends the clocks point-to-point as well as the data, then you only need to configure the control board correctly. Your device boards will have a clock-to-data expecation, eg., centered or edge aligned. All you need to do is have the host transmit data and clocks in that format. 

 

If the control and device boards all use FPGAs for the LVDS interface, then you can use the ALTPLL_RECONFIG to determine how much of an eye pattern opening you have. You do not need external test equipment, though it would be good to look at the waveform shape and differential swing. 

 

Cheers, 

Dave