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"Error 16301 IOPP reference clock is not connected to a clock pin" when trying to use a PLL clock output for EMIF on Arria 10 device

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​Hello,

in a new design I'd like to use Arria 10 External Memory Interface for a DDR3 RAM. The FPGA already has a few input clocks (100 MHz for PCIe refclk, 322 MHz for 10GETH, 40 MHz for core clock generation), so my idea was to generate the emif refclk from an already existing one (my first choice were the 40 MHz). I can generate 83.333 MHz with this one, which is suitable for the emif. But when I try to synthesize the design, it fails with the above emntioned error message and an info line (ID 16302) describing the affected instance.

I have read, that for Cyclone 10 GX devices this option was not enabled, but nothing regarding Arria 10. The *_readme.txt file of the emif even states, that the ref_clk pins are optional.

Do I get something wrong or is it simply not possible to use an internal pll clock for the memory interface?

Best Regards

 

 

 

 

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Moderator
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HI,

 

EMIF DDR3 IP ref_clk pin must comes from FPGA dedicated PLL_clock_in pin for optimum performance and not from another FPGA internal pll clock output source.

 

You can read more about PLL ref clock network architecture in A10 EMIF user guide chapter 3.1.8 (page 23)

 

Thanks.

 

Regards,

dlim

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Highlighted
Moderator
27 Views

HI,

 

EMIF DDR3 IP ref_clk pin must comes from FPGA dedicated PLL_clock_in pin for optimum performance and not from another FPGA internal pll clock output source.

 

You can read more about PLL ref clock network architecture in A10 EMIF user guide chapter 3.1.8 (page 23)

 

Thanks.

 

Regards,

dlim

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