Hi all, I am new to VHDL design and I'm trying to the SDRAM controller code found here http://www.altera.com/products/ip/altera/ocore_sdr_sdram.html.
It appears to be incomplete though. When I try to simulate I get two unbound warnings to missing components "altclklock" and "mt481c8m16a2". Consequently the code does not produce any results.
Does anyone know if these components are available anywhere?
Thanks
