For the Arria 10 transceiver's enhanced standard PCS,
for its pcs rx fifo, there's several mode :
Phase Compensation mode, Register mode, Interlaken mode, 10Gbase-R mode, and basic mode.
Now when I build my requirement simplex RX IP, I only do not need any module in PCS except rx fifo, and I can select phase compensation and basic mode, but I want to whether the rx_control signal is needed for these two mode? And if it is needed, for the tx end, there's no control signal for it, how does it to detect contorl signal and indicate the control data from the rx_control port ? If it is not needed, why is these signal not show unused signal port ?
Could someone help me about this question, thanks.
FPGA chip: 10ax115n2f45e1sg.