FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5741 Discussions

scalable_10GE_MAC_NativePHY_design

mark_lee
New Contributor I
150 Views

I run the example "scalable_10GE_MAC_NativePHY_design" to TEST 1588 PTP ,but I can not get the correct "delay"time and "offset"time . it's still get "0". the output message is:

% TEST_1588 0 1 10G
CONFIGURE CHANNEL 0 as master
configure_to_10G
setting up mac with a basic working config
setting 0xC5C4 into rxmac primary address Reg-1
setting 0xC3C2C1C0 into rxmac primary address Reg-0
enabling: pad and crc stripping in rx mac
testing Configure Period and Adjustment RX XGMII TSU
Configure Period and Adjustment TX XGMII TSU
clearing mac stats registers
testing Configure Period and Adjustment RX XGMII TSU
Configure Period and Adjustment TX XGMII TSU
Configure TOD Master
Configure TOD 10G
Disabling serial PMA Loopback (local)
Read back Serial PMA loopback register = 0x00000000
CONFIGURE CHANNEL 1 as slave
configure_to_10G
setting up mac with a basic working config
setting 0xC5C4 into rxmac primary address Reg-1
setting 0xC3C2C1C0 into rxmac primary address Reg-0
enabling: pad and crc stripping in rx mac
testing Configure Period and Adjustment RX XGMII TSU
Configure Period and Adjustment TX XGMII TSU
clearing mac stats registers
testing Configure Period and Adjustment RX XGMII TSU
Configure Period and Adjustment TX XGMII TSU
Configure TOD Master
Configure TOD 10G
Disabling serial PMA Loopback (local)
Read back Serial PMA loopback register = 0x00000000
Select 1588 traffic controller
Start TOD synchronization
Master 1588 start 1 step operation
TRAFFIC_CONTROLLER_BASE_ADDR: 0x100000
Waiting capturing offset delay ...
Start capturing offset delay ...
Reset Master 1588 start 1 step operation
Reset Start TOD synchronization
delay ns = 0x00000000
delay fns = 0x00000000
offset ns = 0x00000000
offset fns = 0x00000000
===================================================================
| MAC TX STATS REGISTER CHECK
===================================================================
|# FRAMES_RECEIVED_WITH_ERROR = 0
|# UNICAST_FRAMES_WITH_ERROR = 0
|# MULTICAST_FRAMES_RECEIVED_WITH_ERROR = 0
|# BRDCAST_FRAMES_WITH_ERROR = 0
|# FRAMES_RECEIVED_WITH_ONLY_CRCERROR = 0
|# VALID_LENGTH_FRAMES_WITH_CRC_ERROR = 0
|# JABBER_FRAMES = 0
|# FRAGMENTED_FRAMES = 0
|# INVALID_FRAMES_RECEIVED = 0
|# FRAMES_RECEIVED_GOOD = 879546
|# PAUSE_FRAMES_RECEIVED = 0
|# UNICAST_CONTROL_FRAMES = 0
|# MULTICAST_CONTROL_FRAMES = 0
|# UNICAST_FRAMES_RECEIVED_GOOD = 879546
|# MULTICAST_FRAMES_RECEIVED_GOOD = 0
|# BRDCAST_FRAMES_GOOD = 0
|# DATA_AND_PADDING_OCTETS_RECEIVED_GOOD= 43977300
|# COMPREHENSICE_OCTETS_RECEIVED = 59809128
|# FRAMES_WITH_SIZE_64_BYTES = 439773
|# FRAMES_BETWEEN_SIZE_64AND127_BYTES = 439773
|# FRAMES_BETWEEN_SIZE_128AND255_BYTES = 0
|# FRAMES_BETWEEN_SIZE_256AND511_BYTES = 0
|# FRAMES_BETWEEN_SIZE_512AND1K_BYTES = 0
|# FRAMES_BETWEEN_SIZE_1KND1518_BYTES = 0

 

0 Kudos
5 Replies
Deshi_Intel
Moderator
135 Views

Hi Mark,

 

Just to quick check with you, are you referring to below example design ?

 

If yes, then have you followed the test procedure as specified in the user guide doc like

  • page 9, clock controller GUI setting
  • Ensure you connect the SMA cable correctly on the correct SMA port on A10 SI kit board. Double check on the differential pair channel positive vs negative pin polarity
  • page 14, Lastly, you can also refer to signal_tap file to assist you in debugging your hardware test result to validate which status signals are failing vs the golden signal_tap result in page 14,15

 

Also, did you modify the ref design itself ?

 

Thanks.

 

Regards,

dlim

mark_lee
New Contributor I
131 Views

Thanks Deshi and team !  I will try.

Deshi_Intel
Moderator
125 Views

Sure, go ahead to try and check it out !


Deshi_Intel
Moderator
118 Views

HI Mark,


I noticed you have another similar forum post on "Helpless about 1588V2"


  1. Does it mean you already got the 1588 ref design working on A10 SOC dev kit board and now moving to test on your own board ?
  2. Also just wonder what changes that you made that got it working on A10 SOC dev kit board ?


Once I understand the situation then I will close this case and we can continue debug discussion on your "Helpless about 1588V2" post.


Thanks.


Regards,

dlim



mark_lee
New Contributor I
117 Views

Hi Deshi and team

 I agree close this case and we can continue debug discussion on your "Helpless about 1588V2"

 

Reply