simulate DDR2 controller with Micron DDR2 Model

[Altera_Forum]

I generated DDR2 controller in QuartusII for MT47H64M16BT-37E (This DDR2 simulation model was downloaded from Micron). However in the modelsim simulation, it failed with the following message: 

 *****************************************************************************  # ** Error: (vish-4014) No objects found matching '/example_top_tb/dut/resynch_clk'. # Executing ONERROR command at macro ./wave.do line 30 # ** Note: Stratix II GX PLL is enabled # Time: 0 ps Iteration: 2 Instance: /example_top_tb/dut/g_stratixpll_ddr_fedback_pll_inst/altpll_component/stratixii_altpll/m1 # ** Note: Stratix II GX PLL is enabled # Time: 0 ps Iteration: 2 Instance: /example_top_tb/dut/g_stratixpll_ddr_pll_inst/altpll_component/stratixii_altpll/m1 # ** Warning: Invalid transition to 'X' detected on PLL input clk. This edge will be ignored. # Time: 0 ps Iteration: 10 Instance: /example_top_tb/dut/g_stratixpll_ddr_fedback_pll_inst/altpll_component/stratixii_altpll/m1/n1 # 16.85 ns LMR settings = BL = ??, CL = ??, DLL reset # example_top_tb.chipsel__0.mem.gen_rtl_model.mem.cmd_task: at time 16850.0 ps ERROR: Load Mode Failure. All banks must be Precharged. # Break at ../ddr2.v line 662 *****************************************************************************  I was wondering if I did anything wrong when generating the controller file. Could anybody help?  Many thanks, xin

[Altera_Forum]

Sorry, just wanna update my simulation progress! 

 I modified the test bench (example_top_tb.vhd) that is provided together with the DDR2 controller, by setting "reset_n" signal low at the beginning 12 clock cycles (previously, it was high for 6 clock cycles, followed by 6 clock cycles' low, then back to high afterwards).   The simulation passed without previous ERROR on "Load Mode Failure". However, the results showed a lot of timing violation problems, for example:  ERROR: tRFC violation during Write. ERROR: tCK(avg) minimum violation by 6.000000 ps. ERROR: tRP violation during Activate to bank 4. ... ...  How could I avoid these violations?  Thanks, Xin

[Altera_Forum]

Alright so these messages are being provided by the Micron DDR2 model to let you know that you (in this case the Altera DDR2 controller) are violating some of the access times. Sometimes these errors can be meaningless particularly when the simulation starts up. 

 However, I would check the parameter settings file for the simulation model and make sure that you have selected a part and speed grade that matches what you've chosen for the Altera DDR2 controller. I'm guessing that is most likely your problem. If you've got the wrong speed grade, you'll likely get these errors.  Jake

[Altera_Forum]

Hi Jake, 

 Thanks for your comments!   I checked Micron's parameter setting file (ddr2_parameters.vh) for the ddr2 simulation model, but didn't see any problems on that. Also, I run the following command in modelsim to compile this ddr2 model.  vlog -work auk_ddr_user_lib +define+sg37E+x16+MAX_MEM ../ddr2.v  I think I was using the correct speed grade for simulation.  The timing violations are everywhere for each ddr2 command issued to the memory, such as ACT, PCH, WR, RD... What should I do?      Xin

[Altera_Forum]

Hello, just wondering if you are using the High-Performance DDR2 Controller or the non-HP controller and are you using the Avalon Bus? 

 thanks, joe

[Altera_Forum]

Hi Joe, 

I am using DDR SDRAM Controller v7.2, but not HP controller.  I am not using Avalon Bus either.  Thanks, Xin